PCF2123 datasheet(23/63 Pages) NXP

23 / 63 page

PCF2123

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 5 — 27 April 2011

23 of 63

NXP Semiconductors

PCF2123

SPI Real time clock/calendar

therefore changing it without setting bit TE = 0 may result in a corrupted value loaded into

the countdown counter which results in an undetermined countdown period for the first

period. The countdown value n will, however, be correctly stored and correctly loaded on

subsequent timer periods.

When the countdown timer flag is set, an interrupt signal on INT will be generated

provided that this mode is enabled. See Section 8.7.2 for details on how the interrupt can

be controlled.

When starting the timer for the first time, the first period will have an uncertainty which is a

result of the enable instruction being generated from the interface clock which is

asynchronous from the timer source clock. Subsequent timer periods will have no such

delay. The amount of delay for the first timer period will depend on the chosen source

clock, see Table 29.

At the end of every countdown, the timer sets the countdown timer flag (bit TF). Bit TF

may only be cleared by software. The asserted bit TF can be used to generate an

interrupt (INT). The interrupt may be generated as a pulsed signal every countdown

period or as a permanently active signal which follows the condition of bit TF. Bit TI_TP is

used to control this mode selection and the interrupt output may be disabled with bit TIE,

see Table 7.

When reading the timer, the current countdown value is returned and not the initial

value n. Since it is not possible to freeze the countdown timer counter during read back, it

is recommended to read the register twice and check for consistent results.

Timer source clock frequency selection of 1 Hz and 1

⁄

60 Hz will be affected by the

Offset_register. The duration of a program period will vary according to when the offset is

initiated. For example, if a 100 s timer is set using the 1 Hz clock as source, then some

100 s periods will contain correction pulses and therefor be longer or shorter depending

on the setting of the Offset_register. See Section 8.9 to understand the operation of the

Offset_register.

8.6.5 Timer flags

When a minute or second interrupt occurs, bit MSF is set logic 1. Similarly, at the end of a

timer countdown or alarm event, bit TF or AF are set logic 1. These bits maintain their

value until overwritten by software. If both countdown timer and minute or second

interrupts are required in the application, the source of the interrupt can be determined by

reading these bits. To prevent one flag being overwritten while clearing another a logical

AND is performed during a write access. A flag is cleared by writing logic 0 whilst a flag is

not cleared by writing logic 1. Writing logic 1 will result in the flag value remaining

unchanged.

Table 29.

First period delay for timer counter value n

Timer source clock

Minimum timer period

Maximum timer period

4.096 kHz

n + 1

64 Hz

n + 1

1 Hz

− 1) + 1⁄

64 Hz

n + 1

⁄

64 Hz

⁄

60 Hz

− 1) + 1⁄

64 Hz

n + 1

⁄

64 Hz

PCF2123 Datasheet(PDF) 23 Page - NXP Semiconductors

PCF2123 Datasheet(HTML) 23 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63

Datasheet Download

Link URL