PCF2123 datasheet(5/63 Pages) NXP

5 / 63 page

PCF2123

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Product data sheet

Rev. 5 — 27 April 2011

5 of 63

NXP Semiconductors

PCF2123

SPI Real time clock/calendar

7.2 Pin description

[1]

The die paddle (exposed pad) is wired to VSS and should be electrically isolated.

[2]

The substrate (rear side of the die) is wired to VSS and should be electrically isolated.

Table 3.

Pin description

Symbol

Description

HVQFN16

(PCF2123BS/1)

TSSOP14

(PCF2123TS/1)

PCF2123Ux

(bare die)

OSCI

oscillator input; high-impedance node; minimize wire length

between quartz and package

OSCO

oscillator output; high-impedance node; minimize wire length

between quartz and package

n.c.

6, 7, 14, 15

3, 11

do not connect and do not use as feed through; connect to

VDD if floating pins are not allowed

TEST

test pin; not user accessible; connect to VSS or leave floating

(internally pulled down)

INT

interrupt output (open-drain; active LOW)

chip enable input (active HIGH) with internal pull down

VSS

5[1]

712[2]

ground

SDO

serial data output, push-pull; high-impedance when not

driving; can be connected to SDI for single wire data line

SDI

serial data input; may float when CE is inactive

SCL

serial clock input; may float when CE is inactive

CLKOE

CLKOUT enable or disable pin; enable is active HIGH

CLKOUT 12

clock output (open-drain)

VDD

supply voltage; positive or negative steps in VDD may affect

oscillator performance; recommend 100 nF decoupling close

to the device (see Figure 29)

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