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R5F36506NFB Datasheet(PDF) 80 Page - Renesas Technology Corp |
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R5F36506NFB Datasheet(HTML) 80 Page - Renesas Technology Corp |
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80 / 115 page ![]() R01DS0031EJ0200 Rev.2.00 Page 80 of 111 Feb 07, 2011 M16C/65 Group 5. Electrical Characteristics Figure 5.16 Timing Diagram BCLK CSi ADi ALE RD Hi-Z DBi BHE Read timing BCLK CSi ADi ALE BHE DBi Write timing Hi-Z Memory Expansion Mode and Microprocessor Mode (in 1 to 3 waits setting and when accessing external area) 1 V = V = 5V CC1 CC2 td(BCLK-CS) 25ns(max.) 0ns(min.) tcyc th(BCLK-AD) td(BCLK-AD) 25ns(max.) td(BCLK-ALE) 15ns(max.) 0ns(min.) th(BCLK-CS) -4ns(min.) th(BCLK-ALE) 0ns(min.) th(RD-AD) td(BCLK-RD) 25ns(max.) 0ns(min.) th(BCLK-RD) {(n+0.5) × t -45}ns(max.) cyc tsu(DB-RD) 0ns(min.) th(RD-DB) td(BCLK-CS) 25ns(max.) 0ns(min.) th(BCLK-CS) tcyc td(BCLK-AD) 25ns(max.) 0ns(min.) th(BCLK-AD) td(BCLK-ALE) 15ns(max.) -4ns(min.) th(BCLK-ALE) (0.5 × t -10)ns(min.) cyc th(WR-AD) tac2(RD-DB) td(BCLK-WR) 25ns(max.) 0ns(min.) th(BCLK-WR) td(BCLK-DB) 40ns(max.) 0ns(min.) th(WR-DB) td(DB-WR) {(n-0.5) × t -40}ns(min.) cyc (0.5 × t -10)ns(min.) cyc t = cyc th(BCLK-DB) n: 1 (when 1 wait) 2 (when 2 waits) 3 (when 3 waits) Measuring conditions V = V = 5V CC1 CC2 Input timing voltage: V = 0.8 V, V = 2.0 V IL IH Output timing voltage: V = 0.4 V, V = 2.4 V OL OH f(BCLK) 40ns(min.) WR, WRL, WRH |
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