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MSP430F449IPZ Datasheet(PDF) 51 Page - Texas Instruments |
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MSP430F449IPZ Datasheet(HTML) 51 Page - Texas Instruments |
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51 / 79 page ![]() MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009 51 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) 12-bit ADC, power supply and input range conditions (see Note 1) PARAMETER TEST CONDITIONS VCC MIN NOM MAX UNIT AVCC Analog supply voltage AVCC and DVCC are connected together, AVSS and DVSS are connected together, V(AVSS) = V(DVSS) = 0 V 2.2 3.6 V V(P6.x/Ax) Analog input voltage range (see Note 2) All P6.0/A0 to P6.7/A7 terminals. Analog inputs selected in ADC12MCTLx register and P6Sel.x=1, 0 ≤ x ≤ 7; V(AVSS) ≤ VP6.x/Ax ≤ V(AVCC) 0 VAVCC V I Operating supply current into AV terminal fADC12CLK = 5.0 MHz ADC12ON 1 REFON 0 2.2 V 0.65 1.3 mA IADC12 into AVCC terminal (see Note 3) ADC12ON = 1, REFON = 0 SHT0=0, SHT1=0, ADC12DIV=0 3 V 0.8 1.6 mA I Operating supply current it AV ti l fADC12CLK = 5.0 MHz ADC12ON = 0, REFON = 1, REF2_5V = 1 3 V 0.5 0.8 mA IREF+ into AVCC terminal (see Note 4) fADC12CLK = 5.0 MHz ADC12ON 0 2.2 V 0.5 0.8 mA (see Note 4) ADC12ON = 0, REFON = 1, REF2_5V = 0 3 V 0.5 0.8 mA CI Input capacitance Only one terminal can be selected at one time, P6.x/Ax 2.2 V 40 pF RI Input MUX ON resistance 0V ≤ VAx ≤ VAVCC 3 V 2000 Ω NOTES: 1. The leakage current is defined in the leakage current table with P6.x/Ax parameter. 2. The analog input voltage range must be within the selected reference voltage range VR+ to VR− for valid conversion results. 3. The internal reference supply current is not included in current consumption parameter IADC12. 4. The internal reference current is supplied via terminal AVCC. Consumption is independent of the ADC12ON control bit, unless a conversion is active. The REFON bit enables to settle the built-in reference before starting an A/D conversion. 12-bit ADC, external reference (see Note 1) PARAMETER TEST CONDITIONS VCC MIN NOM MAX UNIT VeREF+ Positive external reference voltage input VeREF+ > VREF−/VeREF− (see Note 2) 1.4 VAVCC V VREF− /VeREF− Negative external reference voltage input VeREF+ > VREF−/VeREF− (see Note 3) 0 1.2 V (VeREF+ − VREF−/VeREF−) Differential external reference voltage input VeREF+ > VREF−/VeREF− (see Note 4) 1.4 VAVCC V IVeREF+ Static input current 0V ≤VeREF+ ≤ VAVCC 2.2 V/3 V ±1 µA IVREF−/VeREF− Static input current 0V ≤ VeREF− ≤ VAVCC 2.2 V/3 V ±1 µA NOTES: 1. The external reference is used during conversion to charge and discharge the capacitance array. The input capacitance, Ci, is also the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy. 2. The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced accuracy requirements. 3. The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced accuracy requirements. 4. The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with reduced accuracy requirements. |
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