MSP430F449IPZ datasheet(25/79 Pages) TI

25 / 79 page

MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x

MIXED SIGNAL MICROCONTROLLER

SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

interrupt vector addresses

The interrupt vectors and the power-up starting address are located in the address range 0FFFFh to 0FFE0h.

The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.

Table 3. Interrupt Sources, Flags, and Vectors

INTERRUPT SOURCE

INTERRUPT FLAG

SYSTEM INTERRUPT

WORD

ADDRESS

PRIORITY

Power-Up

External Reset

Watchdog

Flash Memory

WDTIFG

KEYV

(see Note 1)

Reset

0FFFEh

15, highest

NMI

Oscillator Fault

Flash Memory Access Violation

NMIIFG (see Notes 1 and 3)

OFIFG (see Notes 1 and 3)

ACCVIFG (see Notes 1 and 3)

(Non)maskable

0FFFCh

Timer_B7†

TBCCR0 CCIFG (see Note 2)

Maskable

0FFFAh

Timer_B7†

TBCCR1 to TBCCR6 CCIFGs

TBIFG (see Notes 1 and 2)

Maskable

0FFF8h

Comparator_A

CAIFG

Maskable

0FFF6h

Watchdog Timer

WDTIFG

Maskable

0FFF4h

USART0 Receive

URXIFG0

Maskable

0FFF2h

USART0 Transmit

UTXIFG0

Maskable

0FFF0h

ADC12 (see Note 4)

ADC12IFG (see Notes 1 and 2)

Maskable

0FFEEh

Timer_A3

TACCR0 CCIFG (see Note 2)

Maskable

0FFECh

Timer_A3

TACCR1 and TACCR2 CCIFGs,

TAIFG (see Notes 1 and 2)

Maskable

0FFEAh

I/O Port P1 (Eight Flags)

P1IFG.0 to P1IFG.7

(see Notes 1 and 2)

Maskable

0FFE8h

USART1 Receive‡

URXIFG1

Maskable

0FFE6h

USART1 Transmit‡

UTXIFG1

Maskable

0FFE4h

I/O Port P2 (Eight Flags)

P2IFG.0 to P2IFG.7

(see Notes 1 and 2)

Maskable

0FFE2h

Basic Timer1

BTIFG

Maskable

0FFE0h

0, lowest

† ’43x(1) uses Timer_B3 with TBCCR0, 1 and 2 CCIFG flags, and TBIFG. ’44x(1) uses Timer_B7 with TBCCR0 CCIFG, TBCCR1 to TBCCR6

CCIFGs, and TBIFG

‡ USART1 is implemented in ’44x(1) only.

NOTES:

1. Multiple source flags

2. Interrupt flags are located in the module.

3. (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable can not disable

it.

4. ADC12 is not implemented in MSP430x43x1 and MSP430x44x1 devices.

MSP430F449IPZ Datasheet(PDF) 25 Page - Texas Instruments

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