8M (1M × 8) Flash Memory

LH28F008SC

9

COMMAND

BUS

CYCLES

REQ'D

FIRST BUS CYCLE

SECOND BUS CYCLE

NOTE

OPER.

1

ADDRESS

2

DATA

3

OPER.

1

ADDRESS

2

DATA

3

Read Array/Reset

1

Write

X

FFH

Read Identifier Codes

Write

X

90HRead

IA

ID4

Read Status Register

2

Write

X

70H

Read

X

SRD

Clear Status Register

1

Write

X

50H

Block Erase

2

Write

BA

20H

Write

BA

D0H

5

Byte Write

2

Write

WA

40H or 10H

Write

WD

5, 6

Block Erase and Byte

Write Suspend

1Write

X

B0H

WA

5

Block Erase and Byte

Write Resume

1Write

X

D0H

5

Set Block Lock-Bit

2

Write

BA

60H

Write

BA

01H

7

Set Master Lock-Bit

2

Write

X

60H

Write

X

F1H

7

Clear Block Lock Bits

2

Write

X

60H

Write

X

D0H

8

NOTES:

1. Bus operations are defined in Bus Definition Table.

2. X = Any valid address within the device.

IA = Idendifier Code Address: see Figure 5.

BA = Address within the block being erased or locked.

WA = Address of memory location to be written.

3. SRD = Data read from status register. See Status Register for a description of the status register bits.

WD = Data to be written at location WA. Data is latched on the rising edge of WE

ID = Data read from identifier codes.

4. Following the Read Identifier Codes command, read operations access manufacturer, device, block lock, and master lock codes.

See Read Identifier Code Command Section for read identifier code data.

5. If the block is locked, RP

write to locked block while RP

6. Either 40H or 10H are recognized by the WSM as the byte write setup.

7. If the master lock-bit is set, RP

lock-bit is not set, a block lock-bit can be set while RP

8. If the master lock-bit is set, RP

block lock-bits. If the master lock-bit is not set, the Clear Block Lock-Bits command can be done while RP

9. Commands other than those shown above are reserved by SHARP for future device implementations and should not be used.