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LPC4350 Datasheet(PDF) 69 Page - NXP Semiconductors |
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LPC4350 Datasheet(HTML) 69 Page - NXP Semiconductors |
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69 / 149 page  LPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Objective data sheet Rev. 3.1 — 5 January 2012 69 of 149 NXP Semiconductors LPC4350/30/20/10 32-bit ARM Cortex-M4/M0 microcontroller [1] The boot loader programs the appropriate pin function at reset to boot using either SSP0 or SPIFI. [1] The boot loader programs the appropriate pin function at reset to boot using either SSP0 of SPIFI. 7.13 Memory mapping The memory map shown in Figure 9 and Figure 10 is global to both the Cortex-M4 and the Cortex-M0 processors and all SRAM is shared between both processors. Each processor uses its own ARM private bus memory map for the NVIC and other system functions. USB1 0 1 1 1 Boot from USB1. SPI (SSP) 1 0 0 0 Boot from SPI flash connected to the SSP0 interface on P3_3 (function SSP0_SCK), P3_6 (function SSP0_MISO), P3_7 (function SSP0_MOSI), and P3_8 (function SSP0_SSEL)[1]. USART3 1 0 0 1 Boot from device connected to USART3 using pins P2_3 and P2_4. Table 4. Boot mode when OTP BOOT_SRC bits are programmed …continued Boot mode BOOT_SRC bit 3 BOOT_SRC bit 2 BOOT_SRC bit 1 BOOT_SRC bit 0 Description Table 5. Boot mode when OPT BOOT_SRC bits are zero Boot mode Pins Description P2_9 P2_8 P1_2 P1_1 USART0 LOW LOW LOW LOW Boot from device connected to USART0 using pins P2_0 and P2_1. SPIFI LOW LOW LOW HIGH Boot from Quad SPI flash connected to the SPIFI interface on P3_3 to P3_8[1]. EMC 8-bit LOW LOW HIGH LOW Boot from external static memory (such as NOR flash) using CS0 and an 8-bit data bus. EMC 16-bit LOW LOW HIGH HIGH Boot from external static memory (such as NOR flash) using CS0 and a 16-bit data bus. EMC 32-bit LOW HIGH LOW LOW Boot from external static memory (such as NOR flash) using CS0 and a 32-bit data bus. USB0 LOW HIGH LOW HIGH Boot from USB0 USB1 LOW HIGH HIGH LOW Boot from USB1. SPI (SSP) LOW HIGH HIGH HIGH Boot from SPI flash connected to the SSP0 interface on P3_3 (function SSP0_SCK), P3_6 (function SSP0_MISO), P3_7 (function SSP0_MOSI), and P3_8 (function SSP0_SSEL)[1]. USART3 HIGH LOW LOW LOW Boot from device connected to USART3 using pins P2_3 and P2_4. |
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