LPC4350 datasheet(80/149 Pages) PHILIPS

80 / 149 page

LPC4350_30_20_10

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Objective data sheet

Rev. 3.1 — 5 January 2012

80 of 149

NXP Semiconductors

LPC4350/30/20/10

32-bit ARM Cortex-M4/M0 microcontroller

• 8 bits to 16 bits per transfer

7.18.4 SSP serial I/O controller

Remark: The LPC4350/30/20/10 contain two SSP controllers.

The SSP controller is capable of operation on a SPI, 4-wire SSI, or Microwire bus. It can

interact with multiple masters and slaves on the bus. Only a single master and a single

slave can communicate on the bus during a given data transfer. The SSP supports full

duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the

slave and from the slave to the master. In practice, often only one of these data flows

carries meaningful data.

7.18.4.1

Features

• Maximum SSP speed of <tbd> Mbit/s (master) or <tbd> Mbit/s (slave)

• Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National

Semiconductor Microwire buses

• Synchronous serial communication

• Master or slave operation

• 8-frame FIFOs for both transmit and receive

• 4-bit to 16-bit frame

• DMA transfers supported by GPDMA

7.18.5 I2C-bus interface

Remark: The LPC4350/30/20/10 each contain two I2C-bus interfaces.

The I2C-bus is bidirectional for inter-IC control using only two wires: a Serial Clock line

(SCL) and a Serial Data line (SDA). Each device is recognized by a unique address and

can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the

capability to both receive and send information (such as memory). Transmitters and/or

receivers can operate in either master or slave mode, depending on whether the chip has

to initiate a data transfer or is only addressed. The I2C is a multi-master bus and can be

controlled by more than one bus master connected to it.

7.18.5.1

Features

• I2C0 is a standard I2C compliant bus interface with open-drain pins. I2C0 also

supports Fast mode plus with bit rates up to 1 Mbit/s.

• I2C1 uses standard I/O pins with bit rates of up to 400 kbit/s (Fast I2C-bus).

• Easy to configure as master, slave, or master/slave.

• Programmable clocks allow versatile rate control.

• Bidirectional data transfer between masters and slaves.

• Multi-master bus (no central master).

• Arbitration between simultaneously transmitting masters without corruption of serial

data on the bus.

• Serial clock synchronization allows devices with different bit rates to communicate via

one serial bus.

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