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HT67F60 Datasheet(PDF) 115 Page - Holtek Semiconductor Inc

Part # HT67F60
Description  TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM
PDF  242 Pages
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Manufacturer  HOLTEK [Holtek Semiconductor Inc]
Direct Link  http://www.holtek.com
Logo HOLTEK - Holtek Semiconductor Inc

HT67F60 Datasheet(HTML) 115 Page - Holtek Semiconductor Inc

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HT67F30/HT67F40/HT67F50/HT67F60
TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM
Rev. 1.50
114
March 06 , 2012
Rev. 1.50
115
March 06 , 2012
TnIO1 and TnIO0 bits in the TMnC1 register. The TM output pin can be selected using the TnIO1
and TnIO0 bits to go high, to go low or to toggle from its present condition when a compare match
occurs from Comparator A. The initial condition of the TM output pin, which is setup after the
TnON bit changes from low to high, is setup using the TnOC bit. Note that if the TnIO1 and TnIO0
bits are zero then no pin change will take place.
Timer/Counter Mode
To select this mode, bits TnM1 and TnM0 in the TMnC1 register should be set to 11 respectively.
The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode
generating the same interrupt flags. The exception is that in the Timer/Counter Mode the TM output
pin is not used. Therefore the above description and Timing Diagrams for the Compare Match
Output Mode can be used to understand its function. As the TM output pin is not used in this mode,
the pin can be used as a normal I/O pin or other pin-shared function.
Counter Value
0x3FF
CCRP
CCRA
TnON
TnPAU
TnPOL
CCRP Int.
Flag TnPF
CCRA Int.
Flag TnAF
TM O/P Pin
Time
CCRP=0
CCRP > 0
Counter overflow
CCRP > 0
Counter cleared by CCRP value
Pause
Resume
Stop
Counter
Restart
TnCCLR = 0; TnM [1:0] = 00
Output pin set to
initial Level Low
if TnOC=0
Output Toggle with
TnAF flag
Note TnIO [1:0] = 10
Active High Output select
Here TnIO [1:0] = 11
Toggle Output select
Output not affected by TnAF
flag. Remains High until reset
by TnON bit
Output Pin
Reset to Initial value
Output controlled by
other pin-shared function
Output Inverts
when TnPOL is high
Compare Match Output Mode — TnCCLR = 0
Note: 1. With TnCCLR=0, a Comparator P match will clear the counter
2. The TM output pin is controlled only by the TnAF flag
3. The output pin is reset to its initial state by a TnON bit rising edge



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