AD5064 datasheet(25/36 Pages) AD

25 / 36 page

Data Sheet

AD5750/AD5750-1/AD5750-2

Rev. D | Page 25 of 36

CURRENT OUTPUT ARCHITECTURE

The voltage input from the analog input VIN pin (0 V to 4.096 V

for AD5750 and 0 V to 2.5 V for the AD5750-1/AD5750-2) is

either converted to a current (see Figure 53), which is then

mirrored to the supply rail so that the application simply sees

a current source output with respect to an internal reference

voltage, or it is buffered and scaled to output a software-selectable

unipolar or bipolar voltage range (see Figure 54). The reference

is used to provide internal offsets for range and gain scaling.

The selectable output range is programmable through the

digital interface.

IOUT

RANGE

SCALING

REXT1

IOUT

RSET

VSS

VDD

REXT2

IOUT

OPEN FAULT

VIN

VREF

RANGE DECODE

FROM INTERFACE

Figure 53. Current Output Configuration

VOUT RANGE

SCALING

VSENSE+

VOUT

VSENSE–

VOUT

SHORT FAULT

RANGE DECODE

FROM INTERFACE

VIN

(0V TO 4.096V)

VREF

Figure 54. Voltage Output

DRIVING INDUCTIVE LOADS

When driving inductive or poorly defined loads, connect a 0.01 µF

capacitor between IOUT and GND. This ensures stability with

loads beyond 50 mH. There is no maximum capacitance limit.

The capacitive component of the load may cause slower settling.

Voltage Output Amplifier

The voltage output amplifier is capable of generating both unipolar

and bipolar output voltages. It is capable of driving a load of 1 kΩ

in parallel with 1.2 µF (with an external compensation capacitor

on the COMP1 and COMP2 pins). The source and sink capabilities

of the output amplifier can be seen in Figure 16. The slew rate

is 2 V/µs.

Internal to the device, there is a 2.5 MΩ resistor connected

between the VOUT and VSENSE+ pins and, similarly, between

the VSENSE− pin and the internal device ground. If a fault

condition occurs, these resistors act to protect the AD5750/

AD5750-1/AD5750-2 by ensuring that the amplifier loop is closed

so that the part does not enter into an open-loop condition.

The VSENSE− pin can work in a common-mode range of ±3 V

with respect to the remote load ground point.

The current and voltage are output on separate pins and cannot

be output simultaneously. This allows the user to tie both the

current and voltage output pins together and configure the end

system as a single channel output.

Driving Large Capacitive Loads

The voltage output amplifier is capable of driving capacitive loads

of up to 1 µF with the addition of a nonpolarized compensation

capacitor between the COMP1 and COMP2 pins.

Without the compensation capacitor, up to 20 nF capacitive loads

can be driven. Care should be taken to choose an appropriate

value for the CCOMP capacitor. This capacitor, while allowing the

AD5750/AD5750-1/AD5750-2 to drive higher capacitive loads

and reduce overshoot, increases the settling time of the part

and, therefore, affects the bandwidth of the system. Considered

values of this capacitor should be in the range 100 pF to 4 nF,

depending on the trade-off required between settling time,

overshoot, and bandwidth.

POWER-ON STATE OF AD5750/AD5750-1/AD5750-2

On power-up, the AD5750/AD5750-1/AD5750-2 sense whether

hardware or software mode is loaded and set the power-up

conditions accordingly.

In software SPI mode, the power-up state of the output is

dependent on the state of the CLEAR pin. If the CLEAR pin is

pulled high, the part powers up, driving an active 0 V on the

output. If the CLEAR pin is pulled low, the part powers up with

the voltage output channel in tristate mode. In both cases, the

current output channel powers up in the tristate condition (0 mA).

This allows the voltage and current outputs to be connected

together, if desired.

To put the part into normal operation, the user must set the

OUTEN bit in the control register to enable the output and, in

the same write, set the output range configuration using the R3

to R0 range bits. If the CLEAR pin is still high (active) during

this write, the part automatically clears to its normal clear state

as defined by the programmed range and by the CLRSEL pin or

the CLRSEL bit (see the Asynchronous Clear (CLEAR) section

for more details). To operate the part in normal mode, take the

CLEAR pin low.

The CLEAR pin is typically driven directly from a microcontroller.

In cases where the power supply for the AD5750/AD5750-1/

AD5750-2 supply may be independent of the microcontroller

power supply, connect a weak pull-up resistor to DVCC or a pull-

down resistor to ground to ensure that the correct power-up

condition is achieved independent of the microcontroller. A

10 kΩ pull-up/pull-down resistor on the CLEAR pin should be

sufficient for most applications.

If hardware mode is selected, the part powers up to the conditions

defined by the R3 to R0 range bits and the status of the OUTEN

or CLEAR pin. It is recommended to keep the output disabled

when powering up the part in hardware mode.

AD5064 Datasheet(PDF) 25 Page - Analog Devices

AD5064 Datasheet(HTML) 25 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

Datasheet Download

Link URL