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Data Sheet

AD5750/AD5750-1/AD5750-2

Rev. D | Page 31 of 36

APPLICATIONS INFORMATION

TRANSIENT VOLTAGE PROTECTION

The AD5750/AD5750-1/AD5750-2 contain ESD protection

diodes that prevent damage from normal handling. The industrial

control environment can, however, subject I/O circuits to much

higher transients. To protect the AD5750/AD5750-1/AD5750-2

from excessively high voltage transients, external power diodes

and a surge current limiting resistor may be required, as shown

in Figure 56. The constraint on the resistor value is that during

normal operation the output level at IOUT must remain within

its voltage compliance limit of AVDD − 2.75 V and the two

protection diodes and resistor must have appropriate power

ratings. Further protection can be added with transient voltage

suppressors, if needed.

IOUT

AVDD

AVSS

RLOAD

AD5750/

AD5750-1/

AD5750-2

Figure 56. Output Transient Voltage Protection

THERMAL CONSIDERATIONS

It is important to understand the effects of power dissipation

on the package and how it affects junction temperature. The

internal junction temperature should not exceed 125°C. The

AD5750/AD5750-1/AD5750-2 are packaged in a 32-lead, 5 mm ×

5 mm LFCSP package. The thermal impedance, θJA, is 28°C/W. It

is important that the devices are not being operated under

conditions that cause the junction temperature to exceed its

junction temperature.

Worst-case conditions occur when the AD5750/AD5750-1/

AD5750-2 are operated from the maximum AVDD (26.4 V) and

are driving the maximum current (24 mA) directly to ground.

The quiescent current of the AD5750/AD5750-1/AD5750-2

should also be taken into account, nominally ~4 mA.

The following calculations estimate maximum power dissipation

under these worst-case conditions and determine the maximum

ambient temperature:

Power Dissipation = 26.4 V × 28 mA = 0.7392 W

Temperature Increase = 28°C × 0.7392 W = 20.7°C

Maximum Ambient Temperature = 125°C − 20.7°C = 104.3°C

These figures assume that proper layout and grounding techniques

are followed to minimize power dissipation, as outlined in the

Layout Guidelines section.

LAYOUT GUIDELINES

In any circuit where accuracy is important, careful consideration

of the power supply and ground return layout helps to ensure the

rated performance. The PCB on which the AD5750/AD5750-1/

AD5750-2 are mounted should be designed so that the AD5750/

AD5750-1/AD5750-2 lie on the analog plane.

The AD5750/AD5750-1/AD5750-2 should have ample supply

bypassing of 10 µF in parallel with 0.1 µF on each supply located

as close to the package as possible, ideally right up against the

device. The 10 µF capacitors are the tantalum bead type. The

0.1 µF capacitor should have low effective series resistance

(ESR) and low effective series inductance (ESI) such as the

common ceramic types, which provide a low impedance path to

ground at high frequencies to handle transient currents due to

internal logic switching.

In systems where there are many devices on one board, it is often

useful to provide some heat sinking capability to allow the power

to dissipate easily.

The AD5750/AD5750-1/AD5750-2 have an exposed paddle

beneath the device. Connect this paddle to the AVSS supply of

the part. For optimum performance, use special considerations to

design the motherboard and to mount the package. For enhanced

thermal, electrical, and board level performance, solder the

exposed paddle on the bottom of the package to the corresponding

thermal land paddle on the PCB. Design thermal vias into the

PCB land paddle area to further improve heat dissipation.

The AVSS plane on the device can be increased (as shown in

Figure 57) to provide a natural heat sinking effect.

AD5750/

AD5750-1/

AD5750-2

AVSS

PLANE

BOARD

Figure 57. Paddle Connection to Board

AD5064 Datasheet(PDF) 31 Page - Analog Devices

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