AD5064 datasheet(30/36 Pages) AD

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AD5750/AD5750-1/AD5750-2

Data Sheet

Rev. D | Page 30 of 36

EXTERNAL CURRENT SETTING RESISTOR

Referring to Figure 1, RSET is an internal sense resistor and is

part of the voltage-to-current conversion circuitry. The nominal

value of the internal current sense resistor is 15 kΩ. To allow for

overrange capability in current mode, the user can also select

the internal current sense resistor to be 14.7 kΩ, giving a nominal

2% overrange capability. This feature is available in the 0 mA to

+20 mA, +4 mA to +20 mA, and ±20 mA current ranges.

The stability of the output current value over temperature is

dependent on the stability of the value of RSET. As a method of

improving the stability of the output current over temperature,

an external low drift resistor can be connected to the REXT1

and REXT2 pins of the AD5750/AD5750-1/AD5750-2, which

can be used instead of the internal resistor. The external resistor

is selected via the input shift register. If the external resistor option

is not used, leave the REXT1 and REXT2 pins floating.

PROGRAMMABLE OVERRANGE MODES

The AD5750/AD5750-1/AD5750-2 contain an overrange mode

for most of the available ranges. The overranges are selected by

configuring the R3, R2, R1, and R0 bits (or pins) accordingly.

In voltage mode, the overranges are typically 20%, providing

programmable output ranges of 0 V to +6 V, 0 V to +12 V, ±6 V,

and ±12 V. The analog input remains the same.

In current mode, the overranges are typically 2%. In current

mode, the overrange capability is available on only three ranges,

0 mA to 20 mA, 0 mA to 24 mA, and 4 mA to 20 mA. For these

ranges, the analog input also remains the same (0 V to 4.096 V

for the AD5750, and 0 V to 2.5 V for the AD5750-1/AD5750-2).

PACKET ERROR CHECKING

To verify that data has been received correctly in noisy environ-

ments, the AD5750/AD5750-1/AD5750-2 offer the option of error

checking based on an 8-bit cyclic redundancy check (CRC-8).

The device controlling the AD5750/AD5750-1/AD5750-2 should

generate an 8-bit frame check sequence using the following

polynomial:

C(x) = x8 + x2 + x1 + 1

This is added to the end of the data-word, and 24 data bits are

sent to the AD5750/AD5750-1/AD5750-2 before taking SYNC

high. If the AD5750/AD5750-1/AD5750-2 receive a 24-bit data

frame, the parts perform the error check when SYNC goes high.

If the check is valid, the data is written to the selected register. If

the error check fails, the FAULT pin goes low, and Bit D3 of the

status register is set. After reading this register, this error flag is

cleared automatically, and the FAULT pin goes high again.

SCLK

SDIN

SYNC

UPDATE ON SYNC HIGH

D15

(MSB)

(LSB)

16-BIT DATA

16-BIT DATA TRANSER—NO ERROR CHECKING

SCLK

SDIN

SYNC

FAULT

UPDATE AFTER SYNC HIGH

ONLY IF ERROR CHECK PASSED

FAULT GOES LOW IF

ERROR CHECK FAILS

D23

(MSB)

(LSB)

16-BIT DATA

8-BIT FCS

16-BIT DATA TRANSER WITH ERROR CHECKING

Figure 55. PEC Error Checking Timing

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