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LTC4253/LTC4253A

425353afe

the start-up cycle, the SS capacitor (CSS) is ramped by a

22μA (28μA for the LTC4253A) current source. The GATE

pin is held low until SS exceeds 20 • VOS = 0.2V. SS is

internally shunted by a 100k RSS which limits the SS pin

voltage to 2.2V (50k resistor and 1.4V for the LTC4253A).

This corresponds to an analog current limit SENSE voltage

of 100mV (60mV for the LTC4253A). If the SS capacitor

is omitted, the SS pin ramps up in about 250μs (140μs

for the LTC4253A). The SS pin is pulled low under any of

the following conditions: UVLO at VIN, UV, OV, during the

initial timing cycle, a circuit breaker fault time-out or the

RESET pin going high.

SENSE (Pin 7): Circuit Breaker/Current Limit Sense Pin.

Load current is monitored by a sense resistor RSconnected

between SENSE and VEE, and controlled in three steps. If

SENSE exceeds VCB (50mV), the circuit breaker compara-

tor activates a (200μA + 8 • IDRN) TIMER pull-up current.

If SENSE exceeds VACL, the analog current-limit amplifier

pulls GATE down to regulate the MOSFET current at VACL/

RS. In the event of a catastrophic short-circuit, SENSE may

overshoot VACL. If SENSE reaches VFCL (200mV), the fast

current-limit comparator pulls GATE low with a strong

pull-down. To disable the circuit breaker and current limit

functions, connect SENSE to VEE.

VEE (Pin 8): Negative Supply Voltage Input. Connect this

pin to the negative side of the power supply.

GATE (Pin 9): N-channel MOSFET Gate Drive Output. This

pin is pulled high by a 50μA current source. GATE is pulled

low by invalid conditions at VIN (UVLO), UV, OV, during the

initial timing cycle, a circuit breaker fault time-out or the

RESET pin going high. GATE is actively servoed to control

the fault current as measured at SENSE. Compensation

capacitor, CC, at GATE stabilizes this loop. A comparator

monitors GATE to ensure that it is low before allowing an

initial timing cycle, then the GATE ramps up after an over-

voltage event or restart after a current limit fault. During

GATE start-up, a second comparator detects GATE within

2.8V of VIN before PWRGD1 can be set and power good

sequencing starts.

DRAIN (Pin 10): Drain Sense Input. Connecting an external

resistor, RDbetweenthispinandtheMOSFET’sdrain(VOUT)

allows voltage sensing below 6.15V (5V for LTC4253A)

and current feedback to TIMER. A comparator detects if

DRAIN is below 2.39V and together with the GATE high

comparator, sets the PWRGD1 flag. If VOUTisaboveVDRNCL,

the DRAIN pin is clamped at approximately VDRNCL. RD

current is internally multiplied by 8 and added to TIMER’s

200μA during a circuit breaker fault cycle. This reduces

the fault time and MOSFET heating.

OV (Pin 11): Overvoltage Input. For the LTC4253, the

threshold at the OV pin is set at 6.15V with 0.3V hys-

teresis. If OV > 6.15V, GATE pulls low. When OV returns

below 5.85V, GATE start-up begins without an initial timing

cycle. The LTC4253A OV threshold is set at 5.09V with

102mV hysteresis. If OV > 5.09V, GATE pulls low. When

OV returns below 4.988V, GATE start-up begins without an

initial timing cycle. If OV occurs in the middle of an initial

timing cycle, the initial timing cycle is restarted after OV

goes away. OV does not reset the latched fault or PWRGD1

flag. The internal UVLO at VIN always overrides OV. A 1nF

to 10nF capacitor at OV prevents transients and switch-

ing noise from affecting the OV thresholds and prevents

glitches at the GATE.

UV (Pin 12): Undervoltage Input. For the LTC4253, the

threshold at the UV pin is set at 3.225V with 0.3V hysteresis.

If UV < 2.925V, PWRGD1 pulls high, both GATE and TIMER

pull low. If UV rises above 3.225V, this initiates an initial

timing cycle followed by GATE start-up. The LTC4253A UV

threshold is set at 3.08V with 324mV hysteresis. If UV <

2.756V, PWRGD1 pulls high, both GATE and TIMER pull

low. If UV rises above 3.08V, this initiates an initial timing

cycle followed by GATE start-up. The internal UVLO at VIN

always overrides UV. A low at UV resets an internal fault

latch. A 1nF to 10nF capacitor at UV prevents transients

and switching noise from affecting the UV thresholds and

prevents glitches at the GATE pin.

PIN FUNCTIONS

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