LM3447MTSLASHNOPB datasheet(15/25 Pages) TI1

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LM3447

AUX

VCC

GATE

RAUX1

RAUX2

QSW

AUX

IAUX

VALLEY

DETECTION

4 s

TIMER

LEB

1.84 s

1.75V

CONTROL

LOGIC

812ms

FAULT

TIMER

OVP

RAMP

14.5 s

VAL

RAMP

FLT2

ENHOLD

RAMP

VAL

VSW

VAUX

VRAMP

2TS

(a)

(b)

2 (10 Hz

12 Hz)R

R EF

IN S

OUT

REC (PK,MIN )

LM3447

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SNOSC65 A – APRIL 2012 – REVISED MAY 2012

For the above relationship to be valid and for PFC, it is necessary to ensure that the energy in the magnetizing

inductor, LM, is reset every switching cycle and the power stage operates in DCM for the reference power level,

PIN, over the entire range of input voltages. Based on this constraint, the transformer magnetizing inductor should

be chosen as

(9)

where n is the transformer primary to secondary turns-ratio, VOUT = VLED is the LED string voltage and

VREC(PK,MIN) is the minimum peak rectified input voltage. For the LM3447 internal circuit implementation, shown in

Figure 23, the reference voltage, VREF = 1V and the feedforward gain, GFF = 10. To ensure a robust design and

to reject manufacturing variations, a margin of 2% to 10% should be provided when designing the transformer for

magnetizing inductance calculated using Equation 9.

A small capacitor, CFF is connected in parallel with the resistor RFF, to create a low pass filter that can attenuate

twice the line frequency component from the sensed input voltage. It is recommended to set the filter pole

frequency between 10–12Hz to provide 20dB attenuation, such that

(10)

Slow integral compensation is achieved by placing a compensation capacitor CCOMP at the output of the GM

amplifier. A capacitor value ranging from 4.7

μF to 10μF is recommended to achieve a low bandwidth loop of 1Hz

to 10Hz, based on the power level and transient response.

AUX CIRCUIT AND VALLEY DETECT

Figure 24. (a) AUX Circuit; (b) Valley Switching Waveforms

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