TMS320TCI100QGLZ datasheet(83/137 Pages) TI1

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TMS320TCI100Q

FIXEDPOINT DIGITAL SIGNAL PROCESSOR

SPRS251E − JUNE 2004 − REVISED JUNE 2006

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

ASYNCHRONOUS MEMORY TIMING

timing requirements for asynchronous memory cycles for EMIFA module†‡§

(see Figure 22 and Figure 23)

NO.

−850

UNIT

NO.

MIN

MAX

UNIT

tsu(EDV-AREH)

Setup time, EDx valid before ARE high

6.5

th(AREH-EDV)

Hold time, EDx valid after ARE high

tsu(ARDY-EKO1H)

Setup time, ARDY valid before ECLKOUTx high

th(EKO1H-ARDY)

Hold time, ARDY valid after ECLKOUTx high

† To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. The ARDY signal is only recognized

two cycles before the end of the programmed strobe time and while ARDY is low, the strobe time is extended cycle-by-cycle. When ARDY is

recognized low, the end of the strobe time is two cycles after ARDY is recognized high. To use ARDY as an asynchronous input, the pulse width

of the ARDY signal should be wide enough (e.g., pulse width = 2E) to ensure setup and hold time is met.

‡ RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are

programmed via the EMIF CE space control registers.

§ These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a

“B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the asynchronous

memory access signals are shown as generic (AOE, ARE, and AWE) instead of AAOE, AARE, and AAWE (for EMIFA) and BAOE, BARE, and

BAWE (for EMIFB)].

switching characteristics over recommended operating conditions for asynchronous memory

cycles for EMIFA module‡§¶# (see Figure 22 and Figure 23)

NO.

PARAMETER

−850

UNIT

NO.

PARAMETER

MIN

MAX

UNIT

tosu(SELV-AREL)

Output setup time, select signals valid to ARE low

RS * E − 1.5

toh(AREH-SELIV)

Output hold time, ARE high to select signals invalid

RH * E − 1.9

td(EKO1H-AREV)

Delay time, ECLKOUTx high to ARE valid

tosu(SELV-AWEL)

Output setup time, select signals valid to AWE low

WS * E − 1.7

toh(AWEH-SELIV)

Output hold time, AWE high to select signals invalid

WH * E − 1.8

td(EKO1H-AWEV)

Delay time, ECLKOUTx high to AWE valid

1.3

7.1

‡ RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are

programmed via the EMIF CE space control registers.

§ These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a

“B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the asynchronous

memory access signals are shown as generic (AOE, ARE, and AWE) instead of AAOE, AARE, and AAWE (for EMIFA) and BAOE, BARE, and

BAWE (for EMIFB)].

¶ E = ECLKOUT1 period in ns for EMIFA or EMIFB

# Select signals for EMIFA include: ACEx, ABE[7:0], AEA[22:3], AAOE; and for EMIFA writes, include AED[63:0].

Select signals EMIFB include: BCEx, BBE[1:0], BEA[20:1], BAOE; and for EMIFB writes, include BED[15:0].

TMS320TCI100QGLZ Datasheet(PDF) 83 Page - Texas Instruments

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