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TMS320TCI100QGLZ Datasheet(PDF) 1 Page - Texas Instruments |
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TMS320TCI100QGLZ Datasheet(HTML) 1 Page - Texas Instruments |
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1 / 137 page  TMS320TCI100Q FIXEDPOINT DIGITAL SIGNAL PROCESSOR SPRS251E − JUNE 2004 − REVISED JUNE 2006 1 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 D Highest-Performance Fixed-Point Digital Signal Processors (DSPs) − 1.18-ns Instruction Cycle Time − 850-MHz Clock Rate − Eight 32-Bit Instructions/Cycle − Twenty-Eight Operations/Cycle − 6800 MIPS − Fully Software-Compatible With C62x − TCI100/C6416 Pin-Compatible − Extended Temperature Device Available D VelociTI.2 Extensions to VelociTI Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x DSP Core − Eight Highly Independent Functional Units With VelociTI.2 Extensions: − Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle − Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle − Non-Aligned Load-Store Architecture − 64 32-Bit General-Purpose Registers − Instruction Packing Reduces Code Size − All Instructions Conditional D Instruction Set Features − Byte-Addressable (8-/16-/32-/64-Bit Data) − 8-Bit Overflow Protection − Bit-Field Extract, Set, Clear − Normalization, Saturation, Bit-Counting − VelociTI.2 Increased Orthogonality D VCP − Supports Over 600 7.95-Kbps AMR − Programmable Code Parameters D TCP − Supports up to Seven 2-Mbps 3GPP (6 Iterations) − Programmable Turbo Code and Decoding Parameters D L1/L2 Memory Architecture − 128K-Bit (16K-Byte) L1P Program Cache (Direct Mapped) − 128K-Bit (16K-Byte) L1D Data Cache (2-Way Set-Associative) − 8M-Bit (1024K-Byte) L2 Unified Mapped RAM/Cache (Flexible Allocation) D Two External Memory Interfaces (EMIFs) − One 64-Bit (EMIFA), One 16-Bit (EMIFB) − Glueless Interface to Asynchronous Memories (SRAM and EPROM) and Synchronous Memories (SDRAM, SBSRAM, ZBT SRAM, and FIFO) − 1280M-Byte Total Addressable External Memory Space D Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels) D Host-Port Interface (HPI) − User-Configurable Bus Width (32-/16-Bit) D 32-Bit/33-MHz, 3.3-V PCI Master/Slave Interface Conforms to PCI Specification 2.2 − Three PCI Bus Address Registers: Prefetchable Memory Non-Prefetchable Memory I/O − Four-Wire Serial EEPROM Interface − PCI Interrupt Request Under DSP Program Control − DSP Interrupt Via PCI I/O Cycle D Three Multichannel Buffered Serial Ports − Direct Interface to T1/E1, MVIP, SCSA Framers − Up to 256 Channels Each − ST-Bus-Switching-, AC97-Compatible − Serial Peripheral Interface (SPI) Compatible (Motorola ) D Three 32-Bit General-Purpose Timers D UTOPIA − UTOPIA Level 2 Slave ATM Controller − 8-Bit Transmit and Receive Operations up to 50 MHz per Direction − User-Defined Cell Format up to 64 Bytes D Sixteen General-Purpose I/O (GPIO) Pins D Flexible PLL Clock Generator D IEEE-1149.1 (JTAG†) Boundary-Scan-Compatible D 532-Pin Ball Grid Array (BGA) Package (GLZ, ZLZ and CLZ Suffixes), 0.8-mm Ball Pitch D 0.09-µm/7-Level Cu Metal Process (CMOS) D 3.3-V I/Os, 1.2-V Internal (850 MHz) Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 2006, Texas Instruments Incorporated C62x, VelociTI.2, VelociTI, and TMS320C64x are trademarks of Texas Instruments. Motorola is a trademark of Motorola, Inc. † IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture. |
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