TMS320TCI100QGLZ datasheet(95/137 Pages) TI1

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TMS320TCI100Q

FIXEDPOINT DIGITAL SIGNAL PROCESSOR

SPRS251E − JUNE 2004 − REVISED JUNE 2006

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

SYNCHRONOUS DRAM TIMING (CONTINUED)

ECLKOUTx

CEx

ABE[7:0] or BBE[1:0]

AEA[12:3] or BEA[10:1]

AED[63:0] or BED[15:0]

AOE/SDRAS/SOE‡

ARE/SDCAS/SADS/SRE‡

AWE/SDWE/SWE‡

AEA13 or BEA11

AEA[22:14] or BEA[20:12]

BE1

BE2

BE3

BE4

Bank

Column

WRITE

PDT§

† These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a

“B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the synchronous DRAM

memory access signals are shown as generic ( SDCAS, SDWE, and SDRAS ) instead of ASDCAS, ASDWE, and ASDRAS (for EMIFA) and

BSDCAS, BSDWE, and BSDRAS (for EMIFB)].

‡ ARE/SDCAS/SADS/SRE, AWE/SDWE/SWE, and AOE/SDRAS/SOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM

accesses.

§ PDT signal is only asserted when the EDMA is in PDT mode (set the PDTD bit to 1 in the EDMA options parameter RAM). For PDT write, data

is not driven (in High-Z). The PDTWL field in the PDT control register (PDTCTL) configures the latency of the PDT signal with respect to the data

phase of a write transaction. The latency of the PDT signal for a write transaction can be programmed to 0, 1, 2, or 3 by setting PDTWL to 00,

01, 10, or 11, respectively. PDTWL equals 00 (zero latency) in Figure 28.

Figure 28. SDRAM Write Command for EMIFA and EMIFB†

TMS320TCI100QGLZ Datasheet(PDF) 95 Page - Texas Instruments