SC9301 datasheet(18/29 Pages) SEMTECH

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SC9301

AGND

ENL low

threshold

(min 0.4V)

1.57V

LDO on

LDO off

VIN UVLO hysteresis

ENL voltage

Switcher on if EN = high

Switcher off by VIN UVLO

Figure 7 — ENL Thresholds

ENL Logic Control of PWM Operation

When the ENL input exceeds the VIN UVLO threshold of

1.57V, internal logic checks the PGOOD signal. If PGOOD

is high, the switcher is already running and the LDO will

start without affecting the switcher. If PGOOD is low, the

device disables PWM switching until the LDO output has

reached 90% of its final value. This delay prevents the

additional current needed by the DH and DL gate drives

from overloading the LDO at start-up.

LDO Start-up

Before LDO start-up, the device checks the status of the

following signals to ensure proper operation can be

maintained.

ENL pin

VLDO output

input voltage

When the ENL pin is high and V

is available, the LDO will

begin start-up. During the initial phase, when VLDO is

below 1V, the LDO initiates a current-limited start-up

(typically 20mA). This protects the LDO from thermal

damage if the V

LDO

is shorted to ground. As V

LDO

exceeds

1V, the start-up current gradually increases to 115mA.

When V

LDO

reaches 4.5V, the LDO current limit is increased

to 200mA and the LDO output rises quickly to 5.0V. The

LDO start-up is shown in Figure 8.

4.5V

20mA constant current

voltage regulating with

200mA current limit

1.0V

VLDO

increasing current

Figure 8 — LDO Start-Up

Using the Internal LDO to Bias the SC9301

The following steps must be followed when using the

internal LDO to bias the device.

Connect VDD to VLDO before enabling the

LDO.

During the initial start-up the LDO, when the

LDO output is less than 1V, the external load

should not exceed 20mA. Above 1V, any exter-

nal load on VLDO should not exceed 115mA

until the LDO voltage has reached 90% of final

value.

•

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