SC9301 datasheet(22/29 Pages) SEMTECH

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SC9301

Applications Information (continued)

OUT

MIN

Using Ceramic Output Capacitors

When the system is using high ESR value capacitors, the

feedback voltage ripple lags the phase node voltage by 90

degrees. Therefore, the converter is easily stabilized.

When the system is using ceramic output capacitors, the

ESR value is normally too small to meet the above ESR cri-

teria. As a result, the feedback voltage ripple is 180

degrees from the phase node and behaves in an unstable

manner. In this application it is necessary to add a small

virtual ESR network that is composed of two capacitors

and one resistor, as shown in Figure 10.

COUT

DCR

D x VIN

Figure 10 — Virtual ESR Ramp Circuit

The ripple voltage at FB is a superposition of two voltage

sources: the voltage across C

and output ripple voltage.

They are defined in the following equations.

)

DCR

(

DCR

OUT

Figure 11 shows the magnitude of the ripple contribution

due to C

at the FB pin.

DCR

D x VIN

Figure 11 — FB Voltage by CL Voltage

It is shown by the following equation.

VFBc

Figure 12 shows the magnitude of the ripple contribution

due to the output voltage ripple at the FB pin.

COUT

DCR

VOUT

COUT

Figure 12 — FB Voltage by Output Voltage

It is shown by the following equation.

OUT

VFB

The purpose of this network is to couple the inductor

current ripple information into the feedback voltage such

that the feedback voltage has 90 degrees phase lag to the

switching node similar to the case of using standard high

ESR capacitors. This is illustrated in Figure 13.

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