SC9301 datasheet(23/29 Pages) SEMTECH

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SC9301

Applications Information (continued)

VOUT

FB contribution

by CL

FB contribution by

output voltage ripple

Combined FB

Figure 13 — FB voltage in Phasor Diagram

The magnitude of the feedback ripple voltage, which is

dominated by the contribution from C

, is controlled by

the value of R

, R

and C

. If the corner frequency of (R

) x C

is too high, the ripple magnitude at the FB pin will

be smaller, which can lead to double-pulsing. Conversely,

if the corner frequency of (R

// R

) x C

is too low, the ripple

magnitude at FB pin will be higher. Since the SC9301

regulates to the valley of the ripple voltage at the FB pin,

a high ripple magnitude is undesirable as it significantly

impacts the output voltage regulation. As a result, it is

desirable to select a corner frequency for (R

// R

) x C

achieve enough, but not excessive, ripple magnitude and

phase margin. The component values for R

, R

, and C

should be calculated using the following procedure.

Select C

(typical 10nF) and R

to match with L and DCR

time constant using the following equation.

DCR

Select C

by using the following equation.

The resistor values (R

and R

) in the voltage divider circuit

set the V

OUT

for the switcher. The typical value for C

from 10pF to 1nF.

Dropout Performance

The output voltage adjust range for continuous-conduc-

tion operation is limited by the fixed 250ns (typical)

minimum off-time of the one-shot. When working with

low input voltages, the duty-factor limit must be calcu-

lated using worst-case values for on and off times.

The duty-factor limitation is shown by the following

equation.

)

MAX

(

OFF

)

MIN

(

)

MIN

(

DUTY

The inductor resistance and MOSFET on-state voltage

drops must be included when performing worst-case

dropout duty-factor calculations.

System DC Accuracy (V

OUT Controller)

Three factors affect V

OUT

accuracy: the trip point of the FB

error comparator, the ripple voltage variation with line

and load, and the external resistor tolerance. The error

comparator offset is trimmed so that under static condi-

tions it trips when the feedback pin is 600mV, + 1%.

The on-time pulse from the SC9301 in the design example

is calculated to give a pseudo-fixed frequency of 250kHz.

Some frequency variation with line and load is expected.

This variation changes the output ripple voltage. Because

adaptive on-time converters regulate to the valley of the

output ripple, ½ of the output ripple appears as a DC regu-

lation error. For example, if the output ripple is 50mV with

= 6 volts, then the measured DC output will be 25mV

above the comparator trip point. If the ripple increases to

80mV with V

= 25V, then the measured DC output will be

40mV above the comparator trip. The best way to mini-

mize this effect is to minimize the output ripple.

To compensate for valley regulation, it may be desirable to

use passive droop. Take the feedback directly from the

output side of the inductor and place a small amount of

trace resistance between the inductor and output capaci-

tor. This trace resistance should be optimized so that at

full load the output droops to near the lower regulation

limit. Passive droop minimizes the required output capaci-

tance because the voltage excursions due to load steps

are reduced as seen at the load.

The use of 1% feedback resistors contributes up to 1%

error. If tighter DC accuracy is required, 0.1% resistors

should be used.

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