CXD3017Q datasheet(82/117 Pages) SONY

82 / 117 page

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CXD3017Q

§4-16. PWM Output

FCS, TRK and SLD PWM format outputs are described below.

In particular, FCS and TRK use a double oversampling noise shaper.

Timing Chart 4-20 and Fig. 4-21 show examples of output waveforms and drive circuits.

tMCK =

≈ 180ns

Timing Chart 4-20

Fig. 4-21. Drive Circuit

64tMCK

AtMCK

SFDR

SRDR

SLD

32tMCK

FCS/TRK

FFDR/

TFDR

FRDR/

TRDR

Output value +A

Output value –A

Output value 0

tMCK

MCK

(5.6448MHz)

↑ ↑ ↑ ↑ ↑ ↑ ↑

5.6448MHz

VEE

DRV

VCC

RDR

FDR

§4-15. Writing to Coefficient RAM

The coefficient RAM can be rewritten by $34. All coefficients have default values in the built-in ROM, and

transfer from the ROM to the RAM is completed approximately 40µs (when MCK = 128Fs) after the XRST pin

rises. (The coefficient RAM cannot be rewritten during this period.)

After that, the characteristics of each built-in filter can be finely adjusted by rewriting the data for each address

of the coefficient RAM.

The coefficient rewrite command is comprised of 24 bits, with D14 to D8 of $34 as the address (D15 = 0) and

D7 to D0 as the data. Coefficient rewriting is completed 11.3µs (when MCK = 128Fs) after the command is

received. When rewriting multiple coefficients continuously, be sure to wait 11.3µs (when MCK = 128Fs)

before sending the next rewrite command.

CXD3017Q Datasheet(PDF) 82 Page - Sony Corporation

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