STA369BW datasheet(53/88 Pages) STMICROELECTRONICS

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STA369BW

Doc ID 022033 Rev 1

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7.8

Audio preset registers (addr 0x0B and 0x0C)

7.8.1

Audio preset register 1 (addr 0x0B)

Using AMGC[3:0] bits, attack and release thresholds and rates are automatically configured

to properly fit application specific configurations. AMGC[3:2] is defined in register EQ

coefficients and DRC configuration register (addr 0x31) on page 71.

The AMGC[1:0] bits behave in two different ways depending on the value of AMGC[3:2].

When this value is 00, then bits AMGC[1:0] are defined as in Table 54.

Table 53.

Channel volume as a function of CxV[7:0]

CxV[7:0]

Volume

00000000 (0x00)

+48 dB

00000001 (0x01)

+47.5 dB

00000010 (0x02)

+47 dB

……

01011111 (0x5F)

+0.5 dB

01100000 (0x60)

0 dB

01100001 (0x61)

-0.5 dB

……

11010111 (0xD7)

-59.5 dB

11011000 (0xD8)

-60 dB

11011001 (0xD9)

-61 dB

11011010 (0xDA)

-62 dB

……

11101100 (0xEC)

-80 dB

11101101 (0xED)

Hard channel mute

……

11111111 (0xFF)

Hard channel mute

Reserved

AMGC[1]

AMGC[0]

Reserved

Table 54.

Audio preset gain compression/limiters selection for AMGC[3:2] = 00

AMGC[1:0]

Mode

User-programmable GC

AC no clipping 2.1

AC limited clipping (10%) 2.1

DRC nighttime listening mode 2.1

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