STA369BW datasheet(82/88 Pages) STMICROELECTRONICS

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Application

STA369BW

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Doc ID 022033 Rev 1

Application

8.1

Application scheme for power supplies

Figure 33 illustrates the typical application scheme for the STA369BW concerning the power

supplies. Particular care must be given to the layout of the PCB. In particular the 3.3 ohm

resistors on the digital supplies (VDD_DIG) have to be put as close as possible to the device

which avoids any unwanted oscillation on the digital portion of the device due to inductive

traces of the PCB. The same rule is also valid for all the decoupling capacitors in order to

limit spikes on all the supplies.

Figure 33.

Application scheme for power supplies

8.2

PLL filter schematic

It is recommended to use the above scheme and values for the PLL loop filter to achieve the

best performances from the device in general applications. Please note that the ground of

this filter scheme has to be connected to the ground of the PLL without any resistive path.

Concerning the component values, please take into account that the greater the filter

bandwidth, the less the lock time, but the higher the PLL output jitter.

8.3

Typical output configuration

Figure 34 shows the typical output configuration used for BTL stereo mode. Please refer to

the application note for all the other recommended schematics of the output configuration.

AM045198v1

STA369BW Datasheet(PDF) 82 Page - STMicroelectronics