AD7450ARM datasheet(17/24 Pages) AD

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PRELIMINARY TECHNICAL DATA

–17–

AD7450

Figure 19. Serial interface Timing Diagram

2345

t 3

DB11

DB10

DB2

DB1

DB0

t 2

4 LEADING ZERO’S

3-STATE

t 4

t 6

t 5

t 7

QUIET

CONVE RT

SCLK

SDATA

EXTERNAL

VREF (2.5V)

VIN

+2.5V

-2.5V

0.1µF

VREF

VIN+

AD7450

VIN-

+2.5V

+5V

Figure 18. Applying a Bipolar Single Ended Input to the

AD7450

SERIAL INTERFACE

Figure 19 shows a detailed timing diagram for the serial

interface of the AD7450.

The serial clock provides the

conversion clock and also controls the transfer of data

from the AD7450 during conversion.

CS initiates the

conversion process and frames the data transfer.

The fall-

ing edge of

CS puts the track and hold into hold mode

and takes the bus out of three-state.

The analog input is

sampled and the conversion initiated at this point.

The

conversion will require 16 SCLK cycles to complete.

Once 13 SCLK falling edges have occurred, the track and

hold will go back into track on the next SCLK rising edge

as shown at point B in Figure 19.

On the 16th SCLK

falling edge the SDATA line will go back into three-state.

If the rising edge of

CS occurs before 16 SCLKs have

elapsed, the conversion will be terminated

and the SDATA

line will go back into three-state on the 16th SCLK falling

edge. 16 serial clock cycles are required to perform a

conversion and to access data from the AD7450.

CS going

low provides the first leading zero to be read in by the micro-

controller or DSP.

The remaining data is then clocked out

on the subsequent SCLK falling edges beginning with the

second leading zero. Thus the first falling clock edge on the

serial clock provides the second leading zero.

The final bit

in the data transfer is valid on the 16th falling edge, having

been clocked out on the previous (15th) falling edge.

In applications with a slower SCLK, it may be possible to

read in data on each SCLK rising edge i.e. the first rising

edge of SCLK after the

CS falling edge would have the

leading zero provided and the 15th SCLK edge would have

DB0 provided.

Timing Example 1

Having FSCLK = 18MHz and a throughput rate of

1MSPS gives a cycle time of:

1/Throughput = 1/1000000 = 1µs

A cycle consists of:

t2 + 12.5 (1/FSCLK) + tACQ = 1µs.

Therefore if t2 = 10ns then:

10ns + 12.5(1/18MHz) + tACQ = 1µs

tACQ = 296ns

This 296ns satisfies the requirement of 275ns for tACQ.

From Figure 20, tACQ comprises of:

2.5(1/FSCLK) + t8 + tQUIET

where t8 = 45ns. This allows a value of 113ns for tQUIET

satisfying the minimum requirement of 100ns.

Timing Example 2

Having FSCLK = 5MHz and a throughput rate of

315kSPS gives a cycle time of :

1/Throughput = 1/315000 = 3.174µs

A cycle consists of:

t2 + 12.5 (1/FSCLK) + tACQ = 3.174µs.

Therefore if t2 is 10ns then:

10ns + 12.5(1/5MHz) + tACQ = 3.174µs

tACQ = 664ns

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