JS28F128J3C120 datasheet(16/72 Pages) INTEL

16 / 72 page

28F256J3, 28F128J3, 28F640J3, 28F320J3

Datasheet

4.4

Signal Descriptions

Table 3 describes active signals used.

Table 3.

Signal Descriptions (Sheet 1 of 2)

Symbol

Type

Name and Function

Input

BYTE-SELECT ADDRESS: Selects between high and low byte when the device is in x8 mode.

This address is latched during a x8 program cycle. Not used in x16 mode (i.e., the A0 input buffer

is turned off when BYTE# is high).

A[MAX:1]

Input

ADDRESS INPUTS: Inputs for addresses during read and program operations. Addresses are

internally latched during a program cycle.

32-Mbit: A[21:0]

64-Mbit: A[22:0]

128-Mbit: A[23:0]

256-Mbit: A[24:0]

D[7:0]

Input/Output

LOW-BYTE DATA BUS: Inputs data during buffer writes and programming, and inputs

commands during CUI writes. Outputs array, CFI, identifier, or status data in the appropriate read

mode. Data is internally latched during write operations.

D[15:8]

Input/Output

HIGH-BYTE DATA BUS: Inputs data during x16 buffer writes and programming operations.

Outputs array, CFI, or identifier data in the appropriate read mode; not used for Status Register

reads. Data is internally latched during write operations in x16 mode. D[15-8] float in x8 mode

CE0,

CE1,

CE2

Input

CHIP ENABLES: Activates the device’s control logic, input buffers, decoders, and sense

amplifiers. When the device is de-selected (see Table 13 on page 33), power reduces to standby

levels.

All timing specifications are the same for these three signals. Device selection occurs with the

first edge of CE0, CE1, or CE2 that enables the device. Device deselection occurs with the first

edge of CE0, CE1, or CE2 that disables the device (see Table 13 on page 33).

RP#

Input

RESET/ POWER-DOWN: RP#-low resets internal automation and puts the device in power-

down mode. RP#-high enables normal operation. Exit from reset sets the device to read array

mode. When driven low, RP# inhibits write operations which provides data protection during

power transitions.

OE#

Input

OUTPUT ENABLE: Activates the device’s outputs through the data buffers during a read cycle.

OE# is active low.

WE#

Input

WRITE ENABLE: Controls writes to the CUI, the Write Buffer, and array blocks. WE# is active

low. Addresses and data are latched on the rising edge of WE#.

STS

Open Drain

Output

STATUS: Indicates the status of the internal state machine. When configured in level mode

(default), it acts as a RY/BY# signal. When configured in one of its pulse modes, it can pulse to

indicate program and/or erase completion. For alternate configurations of the STATUS signal,

see the Configurations command. STS is to be tied to VCCQ with a pull-up resistor.

BYTE#

Input

BYTE ENABLE: BYTE#-low places the device in x8 mode; data is input or output on D[7:0],

while D[15:8] is placed in High-Z. Address A0 selects between the high and low byte. BYTE#-

high places the device in x16 mode, and turns off the A0 input buffer. Address A1 becomes the

lowest-order address bit.

VPEN

Input

ERASE / PROGRAM / BLOCK LOCK ENABLE: For erasing array blocks, programming data, or

configuring lock-bits.

With VPEN ≤ VPENLK, memory contents cannot be altered.

VCC

Power

CORE POWER SUPPLY: Core (logic) source voltage. Writes to the flash array are inhibited

when VCC ≤ VLKO. Device operation at invalid Vcc voltages should not be attempted.

VCCQ

Power

I/O POWER SUPPLY: I/O Output-driver source voltage. This ball can be tied to VCC.

JS28F128J3C120 Datasheet(PDF) 16 Page - Intel Corporation

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