JS28F128J3C120 datasheet(26/72 Pages) INTEL

26 / 72 page

28F256J3, 28F128J3, 28F640J3, 28F320J3

Datasheet

7.2

Write Operations

Table 9.

Write Operations

Versions

Valid for All

Speeds

Unit

Notes

Symbol

Parameter

Min

Max

tPHWL (tPHEL)

RP# High Recovery to WE# (CEX) Going Low

µs

1,2,3

tELWL (tWLEL)CEX (WE#) Low to WE# (CEX) Going Low

1,2,4

tWP

Write Pulse Width

1,2,4

tDVWH (tDVEH)

Data Setup to WE# (CEX) Going High

1,2,5

tAVWH (tAVEH)

Address Setup to WE# (CEX) Going High

1,2,5

tWHEH (tEHWH)CEX (WE#) Hold from WE# (CEX) High

1,2,

tWHDX (tEHDX)

Data Hold from WE# (CEX) High

1,2,

tWHAX (tEHAX)

Address Hold from WE# (CEX) High

1,2,

tWPH

Write Pulse Width High

1,2,6

W11

tVPWH (tVPEH)VPEN Setup to WE# (CEX) Going High

1,2,3

W12

tWHGL (tEHGL)

Write Recovery before Read

1,2,7

W13

tWHRL (tEHRL)WE# (CEX) High to STS Going Low

500

1,2,8

W15

tQVVL

VPEN Hold from Valid SRD, STS Going High

1,2,3,8,9

NOTES:

CEX low is defined as the first edge of CE0, CE1, or CE2 that enables the device. CEX high is defined at the first edge of CE0, CE1,

or CE2 that disables the device (see Table 13).

1. Read timing characteristics during block erase, program, and lock-bit configuration operations are the same as

during read-only operations. Refer to AC Characteristics–Read-Only Operations.

2. A write operation can be initiated and terminated with either CEX or WE#.

3. Sampled, not 100% tested.

4. Write pulse width (tWP) is defined from CEX or WE# going low (whichever goes low last) to CEX or WE# going

high (whichever goes high first). Hence, tWP = tWLWH = tELEH = tWLEH = tELWH.

5. Refer to Table 14 for valid AIN and DIN for block erase, program, or lock-bit configuration.

6. Write pulse width high (tWPH) is defined from CEX or WE# going high (whichever goes high first) to CEX or WE#

going low (whichever goes low first). Hence, tWPH = tWHWL = tEHEL = tWHEL = tEHWL.

7. For array access, tAVQV is required in addition to tWHGL for any accesses after a write.

8. STS timings are based on STS configured in its RY/BY# default mode.

9. VPEN should be held at VPENH until determination of block erase, program, or lock-bit configuration success

(SR[1,3,4:5] = 0).

JS28F128J3C120 Datasheet(PDF) 26 Page - Intel Corporation

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