LPC4350_13 datasheet(65/153 Pages) NXP

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LPC4350_30_20_10

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Product data sheet

Rev. 4 — 26 March 2013

65 of 153

NXP Semiconductors

LPC4350/30/20/10

32-bit ARM Cortex-M4/M0 microcontroller

7.9.1 Features

• Single selection of a source.

• Signal inversion.

• Can capture a pulse if the input event source is faster than the target clock.

• Synchronization of input event and target clock.

• Single-cycle pulse generation for target.

7.10 On-chip static RAM

The LPC4350/30/20/10 support up to 200 kB local SRAM and an additional 64 kB AHB

SRAM with separate bus master access for higher throughput and individual power

control for low-power operation.

7.11 In-System Programming (ISP)

In-System Programming (ISP) means programming or reprogramming the on-chip SRAM

memory, using the boot loader software and the USART0 serial port. ISP can be

performed when the part resides in the end-user board. ISP loads data into on-chip SRAM

and execute code from on-chip SRAM.

7.12 Boot ROM

The internal ROM memory is used to store the boot code of the LPC4350/30/20/10. After

a reset, the ARM processor will start its code execution from this memory.

The boot ROM memory includes the following features:

• The ROM memory size is 64 kB.

• Supports booting from UART interfaces and external static memory such as NOR

flash, quad SPI flash, and USB0 and USB1.

• Includes API for OTP programming.

• Includes a flexible USB device stack that supports Human Interface Device (HID),

Mass Storage Class (MSC), and Device Firmware Upgrade (DFU) drivers.

Several boot modes are available depending on the values of the OTP bits BOOT_SRC. If

the OTP memory is not programmed or the BOOT_SRC bits are all zero, the boot mode is

determined by the states of the boot pins P2_9, P2_8, P1_2, and P1_1.

Table 4.

Boot mode when OTP BOOT_SRC bits are programmed

Boot mode BOOT_SRC

bit 3

BOOT_SRC

bit 2

BOOT_SRC

bit 1

BOOT_SRC

bit 0

Description

Pin state

Boot source is defined by the reset state of P1_1,

P1_2, P2_8, and P2_9 pins. See Table 5.

USART0

Boot from device connected to USART0 using pins

P2_0 and P2_1.

SPIFI

Boot from Quad SPI flash connected to the SPIFI

interface using pins P3_3 to P3_8.

EMC 8-bit

Boot from external static memory (such as NOR

flash) using CS0 and an 8-bit data bus.

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