LPC4350_13 datasheet(77/153 Pages) NXP

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LPC4350_30_20_10

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Product data sheet

Rev. 4 — 26 March 2013

77 of 153

NXP Semiconductors

LPC4350/30/20/10

32-bit ARM Cortex-M4/M0 microcontroller

transfers, with frames of 4 bit to 16 bit of data flowing from the master to the slave and

from the slave to the master. In practice, often only one of these data flows carries

meaningful data.

7.18.4.1

Features

• Maximum SSP speed in full-duplex mode of 25 Mbit/s; for transmit only 50 Mbit/s

(master) and 17 Mbit/s (slave).

• Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National

Semiconductor Microwire buses

• Synchronous serial communication

• Master or slave operation

• 8-frame FIFOs for both transmit and receive

• 4-bit to 16-bit frame

• DMA transfers supported by GPDMA

7.18.5 I2C-bus interface

Remark: The LPC4350/30/20/10 contain two I2C-bus interfaces.

The I2C-bus is bidirectional for inter-IC control using only two wires: a Serial Clock line

(SCL) and a Serial Data line (SDA). Each device is recognized by a unique address and

can operate as either a receiver-only device (for example an LCD driver) or a transmitter

with the capability to both receive and send information (such as memory). Transmitters

and/or receivers can operate in either master or slave mode, depending on whether the

chip has to initiate a data transfer or is only addressed. The I2C is a multi-master bus and

can be controlled by more than one bus master connected to it.

7.18.5.1

Features

• I2C0 is a standard I2C-compliant bus interface with open-drain pins. I2C0 also

supports Fast mode plus with bit rates up to 1 Mbit/s.

• I2C1 uses standard I/O pins with bit rates of up to 400 kbit/s (Fast I2C-bus).

• Easy to configure as master, slave, or master/slave.

• Programmable clocks allow versatile rate control.

• Bidirectional data transfer between masters and slaves.

• Multi-master bus (no central master).

• Arbitration between simultaneously transmitting masters without corruption of serial

data on the bus.

• Serial clock synchronization allows devices with different bit rates to communicate via

one serial bus.

• Serial clock synchronization can be used as a handshake mechanism to suspend and

resume serial transfer.

• The I2C-bus can be used for test and diagnostic purposes.

• All I2C-bus controllers support multiple address recognition and a bus monitor mode.

7.18.6 I2S interface

Remark: The LPC4350/30/20/10 contain two I2S-bus interfaces.

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