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PCM1716E/2K Datasheet(PDF) 10 Page - Texas Instruments

Part # PCM1716E/2K
Description  24-Bit, 96kHz Sampling CMOS Delta-Sigma Stereo Audio DIGITAL-TO-ANALOG CONVERTER
PDF  18 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

PCM1716E/2K Datasheet(HTML) 10 Page - Texas Instruments

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10
PCM1716
REGISTER
BIT
NAME
NAME
DESCRIPTION
Register 0
AL (7:0)
DAC Attenuation Data for Lch
LDL
Attenuation Data Load Control for Lch
A (1:0)
Register Address
res
Reserved, should be “L”
Register 1
AR (7:0)
DAC Attenuation Data for Rch
LDR
Attenuation Data Load Control for Rch
A (1:0)
Register Address
res
Reserved, should be “L”
Register 2
MUT
Left and Right DACs Soft Mute Control
DEM
De-emphasis Control
OPE
Left and Right DACs Operation Control
IW (1:0)
Input Audio Data Bit and Format Select
res
Reserved
A (1:0)
Register Address
res
Reserved, should be “L”
Register 3
I2S
Audio Data Format Select
LRP
Polarity of LRCIN Select
ATC
Attenuator Control
SRO
Slow Roll-Off Select
REV
Output Phase Select
CKO
CLKO Output Select
SF (1:0)
Sampling Rate Select
IZD
Internal Zero Detection Circuit Control
A (1:0)
Register Address
res
Reserved, should be “L”
TABLE VII. Register Functions
REGISTER 0 (A1 = 0, A0 = 0)
B15 B14 B13 B12 B11 B10 B9 B8
B7 B6
B5
B4 B3
B2
B1 B0
res res res res res A1 A0 LDL AL7 AL6 AL5 AL4 AL3 AL2 AL1 AL0
Register 0 is used to control left channel attenuation. Bits
0 - 7 (AL0 - AL7) are used to determine the attenuation
level. The level of attenuation is given by:
ATT = 0.5 x (data-255) (dB)
FFh = –0dB
FEh = –0.5dB
:
:
01h = –127.5dB
00h = –
∞ (= Mute)
ATTENUATION DATA LOAD CONTROL
Bit 8 (LDL) is used to control the loading of attenuation data
in B0:B7. When LDL is set to 0, attenuation data will be
loaded into AL0:AL7, but it will not affect the attenuation
level until LDL is set to 1. LDR in Register 1 has the same
function for right channel attenuation.
REGISTER 1 (A1 = 0, A0 = 1)
B15 B14 B13 B12 B11 B10 B9 B8
B7 B6
B5
B4 B3
B2
B1 B0
res res res res res A1 A0 LDR AR7 AR6 AR5 AR4 AR3 AR2 AR1 AR0
Register 1 is used to control right channel attenuation. As
in Register 1, bits 0 - 7 (AR0 - AR7) control the level of
attenuation.
Register 2 is used to control soft mute, de-emphasis, opera-
tion enable, input resolution, and input audio data bit and
format.
REGISTER 2 (A1 = 1, A0 = 0)
B15 B14 B13 B12 B11 B10 B9 B8
B7 B6
B5
B4 B3
B2
B1
B0
res res res res res A1 A0 res
res res res IW1 IWO OPE DEM MUTE
when OPE (B2) is “HIGH”, the output of the DAC will be
forced to bipolar zero, irrespective of any input data.
IWO (B3), IW1 (B4) and I2S (B0) of Register 3
These resisters, IWO, IW1, I2S determine the input data
word and input data format as shown below.
IW1
IW0
I2S
Audio Interface
0
0
0
16-Bit Standard (Right-Justified)
0
1
0
20-Bit Standard (Right-Justified)
1
0
0
24-Bit Standard (Right-Justified)
1
1
0
24-Bit Left-Justified (MSB First)
0
0
1
16-Bit I2S
0
1
1
24-Bit I2S
1
0
1
Reserved
1
1
1
Reserved
REGISTER 3 (A1 = 1, A0 = 1)
B15 B14 B13 B12 B11 B10 B9 B8
B7 B6
B5
B4 B3
B2
B1
B0
res res res res res A1 A0 IZD
SF1 SF0 CKO REV SRO ATC LRP I2S
REGISTER 3 (A1 = 1, A0 = 1)
Register 3 is used to control input data format and polarity,
attenuation channel control, system clock frequency, sam-
pling frequency, infinite zero detection, output phase,
CLKO output, and slow roll-off.
Bit 8 is used to control the infinite zero detection function
(IZD).
When IZD is “LOW”, the zero detect circuit is off. Under
this condition, no automatic muting will occur if the input
is continuously zero. When IZD is “HIGH”, the zero detect
feature is enabled. If the input data is continuously zero for
65, 536 cycles of BCKIN, the output will be immediately
MUT (B0)
MUT = L
Soft Mute OFF
MUT = H
Soft Mute ON
OPE (B2)
OPE = L
Normal Operation
OPE = H
DAC Operation OFF
DEM (B1)
DEM = L
De-emphasis OFF
DEM = H
De-emphasis ON
Not Recommended For New Designs



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