TAS5707APHPR datasheet(37/58 Pages) TI1

37 / 58 page

TAS5707, TAS5707A

www.ti.com

SLOS556B – NOVEMBER 2008 – REVISED NOVEMBER 2009

CLOCK CONTROL REGISTER (0x00)

The clocks and data rates are automatically determined by the TAS5707. The clock control register contains the

auto-detected clock status. Bits D7–D5 reflect the sample rate. Bits D4–D2 reflect the MCLK frequency. The

device accepts a 64-fS or 32-fS SCLK rate for all MCLK rates, but accepts a 48-fS SCLK rate for MCLK rates of

192 fS and 384 fS only.

Table 5. Clock Control Register (0x00)

FUNCTION

–

fS = 32-kHz sample rate

–

Reserved(1)

–

Reserved(1)

–

fS = 44.1/48-kHz sample rate

(2)

–

fs = 16-kHz sample rate

–

fs = 22.05/24 -kHz sample rate

–

fs = 8-kHz sample rate

–

fs = 11.025/12 -kHz sample rate

–

MCLK frequency = 64 × fS

(3)

–

MCLK frequency = 128 × fS

(3)

–

MCLK frequency = 192 × fS

(4)

–

MCLK frequency = 256 × fS

(2) (5)

–

MCLK frequency = 384 × fS

–

MCLK frequency = 512 × fS

–

Reserved(1)

–

Reserved(1)

–

Reserved(1)

–

Reserved(1)

(1)

Reserved registers should not be accessed.

(2)

Default values are in bold.

(3)

Only available for 44.1 kHz and 48 kHz rates.

(4)

Rate only available for 32/44.1/48 KHz sample rates

(5)

Not available at 8 kHz

DEVICE ID REGISTER (0x01)

The device ID register contains the ID code for the firmware revision.

Table 6. General Status Register (0x01)

FUNCTION

–

Reserved

–

Identification code

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