TMP86FS49FG datasheet(23/42 Pages) TOSHIBA

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TMP86FS49FG

2.2.4.2 IDLE1/2 mode and SLEEP1/2 mode

IDLE1/2 and SLEEP1/2 modes are controlled by the system control register 2 (SYSCR2) and maskable

interrupts. The following status is maintained during these modes.

1. Operation of the CPU and watchdog timer (WDT) is halted. On-chip peripherals continue to

operate.

2. The data memory, CPU registers, program status word and port output latches are all held in the

status in effect before these modes were entered.

3. The program counter holds the address 2 ahead of the instruction which starts these modes.

Figure 2-10 IDLE1/2 and SLEEP1/2 Modes

(1) Start the IDLE1/2 and SLEEP1/2 modes

When IDLE1/2 and SLEEP1/2 modes start, set SYSCR2<IDLE> to “1”. After IMF is set to "0",

set the individual interrupt enable flag (EF) which releases IDLE1/2 and SLEEP1/2.

(2) Release the IDLE1/2 and SLEEP1/2 modes

IDLE1/2 and SLEEP1/2 modes include a normal release mode and an interrupt release mode.

These modes are selected by interrupt master enable flag (IMF). After releasing IDLE1/2 and

SLEEP1/2 modes, the SYSCR2<IDLE> is automatically cleared to “0” and the operation mode is

returned to the mode preceding IDLE1/2 and SLEEP1/2 modes.

IDLE1/2 and SLEEP1/2 modes can also be released by inputting low level on the RESET pin. After

releasing reset, the operation mode is started from NORMAL1 mode.

Reset

Reset input

Yes (Interrupt release mode)

Yes

Starting IDLE1/2

and SLEEP1/2 modes

by instruction

CPU and WDT are halted

Interrupt request

IMF = 1

Interrupt processing

Execution of the

instruction which follows

the IDLE1/2 and SLEEP1/2

modes start instruction

Normal

release mode

Yes

TENTATIVE

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