TMP86FS49FG datasheet(24/42 Pages) TOSHIBA

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2. Operational Description

2.2 System Clock Controller

TMP86FS49FG

(3) Normal release mode (IMF = “0”)

IDLE1/2 and SLEEP1/2 modes are released by any interrupt source enabled by the individual

interrupt enable flag (EF). After the interrupt is generated, the program operation is resumed from the

instruction following the IDLE1/2 and SLEEP1/2 modes start instruction. Normally, the interrupt

latches (IL) of the interrupt source used for releasing must be cleared to “0” by load instructions.

(4) Interrupt release mode (IMF = “1”)

IDLE1/2 and SLEEP1/2 modes are released by any interrupt source enabled with the individual

interrupt enable flag (EF) and the interrupt processing is started. After the interrupt is processed, the

program operation is resumed from the instruction following the instruction, which starts IDLE1/2

and SLEEP1/2 modes.

Note: When a watchdog timer interrupts is generated immediately before IDLE1/2 and SLEEP1/2 mode

are started, the watchdog timer interrupt will be processed but IDLE1/2 and SLEEP1/2 mode will

not be started.

TENTATIVE

TMP86FS49FG Datasheet(PDF) 24 Page - Toshiba Semiconductor