FLEX10KA datasheet(31/128 Pages) ALTERA

31 / 128 page

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Each IOE selects the clock, clear, clock enable, and output enable controls

from a network of I/O control signals called the peripheral control bus.

The peripheral control bus uses high-speed drivers to minimize signal

skew across devices; it provides up to 12 peripheral control signals that

can be allocated as follows:

■

Up to eight output enable signals

■

Up to six clock enable signals

■

Up to two clock signals

■

Up to two clear signals

If more than six clock enable or eight output enable signals are required,

each IOE on the device can be controlled by clock enable and output

enable signals driven by specific LEs. In addition to the two clock signals

available on the peripheral control bus, each IOE can use one of two

dedicated clock pins. Each peripheral control signal can be driven by any

of the dedicated input pins or the first LE of each LAB in a particular row.

In addition, an LE in a different row can drive a column interconnect,

which causes a row interconnect to drive the peripheral control signal.

The chip-wide reset signal will reset all IOE registers, overriding any other

control signals.

Tables 8 and 9 list the sources for each peripheral control signal, and the

rows that can drive global signals. These tables also show how the output

enable, clock enable, clock, and clear signals share 12 peripheral control

signals.

FLEX10KA Datasheet(PDF) 31 Page - Altera Corporation