AD9920ABBCZ datasheet(49/112 Pages) AD

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AD9920A

Rev. B | Page 49 of 112

Mode Registers

The mode registers are used to select the field timing of the

AD9920A. Typically, all of the field, V-sequence, and V-pattern

information is programmed into the AD9920A at startup. During

operation, the mode registers allow the user to select any combi-

nation of field timing to meet the requirements of the system.

The advantage of using the mode registers in conjunction with

preprogrammed timing is that it greatly reduces the system pro-

gramming requirements during camera operation. Only a few

changed; the vertical timing information does not need to be

changed with each camera mode change.

A basic still camera application can require six fields of vertical

timing—one for draft mode operation, one for autofocusing,

and four for still image readout. All of the register timing informa-

tion for the six fields is loaded at startup. Then, during camera

operation, the mode registers select which field timing is active,

depending on how the camera is being used.

Table 22 shows how the mode registers are used. The mode

Any value from 1 to 7 can be selected using these three bits.

The other two registers (Address 0x2B and Address 0x2C) are

used to select which of the programmed fields are used and in

which order. Up to seven fields can be used in a single write to

the mode register. The AD9920A starts with the field timing

specified by FIELD1, and on the next VD switches to the timing

specified by FIELD2, and so on. After completing the total

number of fields specified by the mode register, the AD9920A

repeats by starting at the first field. This continues until a new

write to the mode register occurs. Figure 61 shows example

mode register settings for different field configurations.

Note that only a write to Address 0x2C properly resets the field

counter. Therefore, when changing the values in any of the mode

registers, it is recommended that all three registers be updated

together in the same field (VD period).

Caution

The mode registers are SCK updated by default. If they are

configured as VD-updated registers by writing Address 0xB4 =

0x03FF and Address 0xB5 = 0xFC00, the new mode informa-

tion is updated on the second VD falling edge after the write

occurs, rather than on the first VD falling edge. See Figure 63

for an example.

Table 22. Mode Registers

Address

Name

Length (Bits)

Description

0x2A

MODE

Total number of fields to cycle through. Set from 1 to 7.

0x2B

FIELD1

Selected field (from FIELD registers in configurable memory) for the first field to cycle through.

FIELD2

Selected field (from FIELD registers in configurable memory) for the second field to cycle through.

FIELD3

Selected field (from FIELD registers in configurable memory) for the third field to cycle through.

FIELD4

Selected field (from FIELD registers in configurable memory) for the fourth field to cycle through.

FIELD5

Selected field (from FIELD registers in configurable memory) for the fifth field to cycle through.

0x2C

FIELD6

Selected field (from FIELD registers in configurable memory) for the sixth field to cycle through.

FIELD7

Selected field (from FIELD registers in configurable memory) for the seventh field to cycle through.

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