AD9920ABBCZ datasheet(19/112 Pages) AD

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AD9920A

Rev. B | Page 19 of 112

H-Driver and RG Outputs

In addition to the programmable timing positions, the AD9920A

features on-chip output drivers for the RG, HL, and H1 to H8

outputs. These drivers are powerful enough to drive the CCD

inputs directly. The H-driver and RG current can be adjusted for

optimum rise/fall time for a particular load by using the drive

strength control registers (Address 0x36 and Address 0x37). The

3-bit drive setting for each H1 to H8 output is adjustable in

4.3 mA increments: 0 = off, 1 = 4.3 mA, 2 = 8.6 mA, 3 = 12.9 mA,

4 = 17.3 mA, 5 = 21.6 mA, 6 = 25.9 mA, and 7 = 30.2 mA.

The 3-bit drive settings for the HL and RG outputs are also

adjustable in 4.3 mA increments, but with a maximum drive

strength of 17.3 mA: 0 = off, 1 = 4.3 mA, 2 = 8.6 mA, 3 = 12.9 mA,

4 = 4.3 mA, 5 = 8.6 mA, 6 = 12.9 mA, and 7 = 17.3 mA.

As shown in Figure 19, when HCLK Mode 1 is used, the H2,

H4, H6, and H8 outputs are inverses of the H1, H3, H5, and H7

outputs. Using the HCLKMODE register (Address 0x24,

Bits[4:0]), it is possible to select a different configuration.

Table 10 shows a comparison of the different programmable

settings for each HCLK mode. Figure 20 and Figure 21 show the

settings for HCLK Mode 2 and HCLK Mode 3, respectively.

It is recommended that all H1 to H8 outputs on the AD9920A be

used together for maximum flexibility in drive strength settings.

A typical CCD with H1 and H2 inputs should have only the

AD9920A H1, H3, H5, and H7 outputs connected together to

drive the CCD H1 and should have only the AD9920A H2, H4,

H6, and H8 outputs connected together to drive the CCD H2.

In 3-phase HCLK mode, only six of the HCLK outputs are used,

with two outputs driving each of the three phases:

•

H1 and H2 are connected to CCD Phase 1.

•

H5 and H6 are connected to CCD Phase 2.

•

H7 and H8 are connected to CCD Phase 3.

Table 9. Timing Core Register Parameters for H1, H2, HL, RG, SHP, and SHD

Parameter

Length (Bits)

Range

Description

Positive Edge

0 to 63 edge location

Positive edge location for H1, H2, HL, H3P1, and RG.

Negative Edge

0 to 63 edge location

Negative edge location for H1, H2, HL, H3P1, and RG.

Sampling Location

0 to 63 edge location

Sampling location for internal SHP and SHD signals.

Drive Strength

0 to 7 current steps

Drive current for H1 to H8, HL, and RG outputs (4.3 mA per step).

Table 10. HCLK Modes, Selected by Address 0x24, Bits[4:0]

HCLKMODE

Description

Mode 1

0x01

H1 edges are programmable with H3 = H5 = H7 = H1, H2 = H4 = H6 = H8 = inverse of H1.

Mode 2

0x02

H1 edges are programmable with H3 = H5 = H7 = H1.

H2 edges are programmable with H4 = H6 = H8 = H2.

Mode 3

0x04

H1 edges are programmable with H3 = H1 and H2 = H4 = inverse of H1.

H5 edges are programmable with H7 = H5 and H6 = H8 = inverse of H5.

3-Phase Mode

0x10

H1 edges are programmable using Address 0x33 and H2 = H1 (Phase 1).

H5 edges are programmable using Address 0x31 and H6 = H5 (Phase 2).

H7 edges are programmable using Address 0x30 and H8 = H7 (Phase 3).

Invalid Selection

All other values

Invalid register settings. Do not use.

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