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AD9920ABBCZ Datasheet(PDF) 8 Page - Analog Devices |
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AD9920ABBCZ Datasheet(HTML) 8 Page - Analog Devices |
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8 / 112 page  AD9920A Rev. B | Page 8 of 112 VERTICAL DRIVER SPECIFICATIONS VH1, VH2 = 12 V; VM1, VM2, VMM = 0 V; VL1, VL2, VLL = −6 V; CL shown in load model; TA = 25°C. Table 5. Parameter Symbol Test Conditions/Comments Min Typ Max Unit V1A TO V13 Simplified load conditions, 3000 pF to ground + 30 Ω in series, SRSW = VSS Delay Time, VL to VM and VM to VH tPLM, tPMH 40 ns Delay Time, VM to VL and VH to VM tPML, tPHM 40 ns Rise Time, VL to VM tRLM 150 ns Rise Time, VM to VH tRMH 315 ns Fall Time, VM to VL tFML 250 ns Fall Time, VH to VM tFHM 165 ns Output Currents At −7.25 V 10 mA At −0.25 V −22 mA At +0.25 V 22 mA At +14.75 V −10 mA RON 35 Ω V14, V15, V16 Simplified load conditions, 3000 pF to ground + 30 Ω in series Delay Time, VL to VM tPLM 45 ns Delay Time, VM to VL tPML 45 ns Rise Time, VL to VM tRLM 345 ns Fall Time, VM to VL tFML 280 ns Output Currents At −7.25 V 10 mA At −0.25 V −7 mA RON 55 Ω SUBCK OUTPUT Simplified load conditions, 1000 pF to ground Delay Time, VLL to VH tPLH 50 ns Delay Time, VH to VLL tPHL 50 ns Delay Time, VLL to VMM tPLM 50 ns Delay Time, VMM to VH tPMH 50 ns Delay Time, VH to VMM tPHM 50 ns Delay Time, VMM to VLL tPML 50 ns Rise Time, VLL to VH tRLH 50 ns Rise Time, VLL to VMM tRLM 55 ns Rise Time, VMM to VH tRMH 50 ns Fall Time, VH to VLL tFHL 55 ns Fall Time, VH to VMM tFHM 100 ns Fall Time, VMM to VLL tFML 40 ns Output Currents At −7.25 V 20 mA At −0.25 V −12 mA At +0.25 V 12 mA At +14.75 V −20 mA RON 35 Ω SRCTL INPUT RANGE Valid only when SRSW is high 0.8 VDVDD V |
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