MPC8321VRADDC datasheet(10/82 Pages) FREESCALE

10 / 82 page

MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4

Freescale Semiconductor

Clock Input Timing

NOTE

AVDDn (1.0 V) is estimated to consume 0.05 W (under normal operating

conditions and ambient temperature).

Clock Input Timing

This section provides the clock input DC and AC electrical characteristics for the MPC8323E.

NOTE

The rise/fall time on QUICC Engine input pins should not exceed 5 ns. This

should be enforced especially on clock signals. Rise time refers to signal

transitions from 10% to 90% of VCC; fall time refers to transitions from

90% to 10% of VCC.

4.1

DC Electrical Characteristics

Table 7 provides the clock input (CLKIN/PCI_SYNC_IN) DC timing specifications for the MPC8323E.

Local bus I/O

load = 25 pF

1 pair of clocks

66 MHz, 32 bits

—

0.12

—

PCI I/O load = 30 pF

66 MHz, 32 bits

—

0.057

—

QUICC Engine block and

other I/Os

UTOPIA 8-bit 31 PHYs

—

0.041

Multiply by

number of

interfaces used.

TDM serial

—

0.001

TDM nibble

—

0.004

HDLC/TRAN serial

—

0.003

HDLC/TRAN nibble

—

0.025

DUART

—

0.017

MIIs

—

0.009

RMII

—

0.009

Ethernet management

—

0.002

USB

—

0.001

SPI

—

0.001

Timer output

—

0.002

Table 7. CLKIN DC Electrical Characteristics

Parameter

Condition

Symbol

Min

Max

Unit

Input high voltage

—

VIH

2.7

OVDD +0.3

Input low voltage

—

VIL

–0.3

0.4

Table 6. Estimated Typical I/O Power Dissipation (continued)

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