- (T1)

2

)

(

1

)

(

LM5045

SNVS699G – FEBRUARY 2011 – REVISED MARCH 2013

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Soft-Start

The soft-start circuit allows the power converter to gradually reach a steady state operating point, thereby

reducing the start-up stresses and current surges. When bias is supplied to the LM5045, the SS capacitor is

discharged by an internal MOSFET. When the UVLO, VCC and REF pins reach their operating thresholds, the

SS capacitor is released and is charged with a 20µA current source. Once the SS pin voltage crosses the 1V

offset, SS controls the duty cycle. The PWM comparator is a three input device; it compares the RAMP signal

against the lower of the signals between the soft-start and the loop error signal. In a typical isolated application,

as the secondary bias is established, the error amplifier on the secondary side soft-starts and establishes closed-

loop control, steering the control away from the SS pin.

One method to shutdown the regulator is to ground the SS pin. This forces the internal PWM control signal to

ground, reducing the output duty cycle quickly to zero. Releasing the SS pin begins a soft-start cycle and normal

operation resumes. A second shutdown method is presented in the UVLO section.

Gate Driver Outputs

The LM5045 provides four gate drivers: two floating high side gate drivers HO1 and HO2 and two ground

referenced low side gate drivers LO1 and LO2. Each internal driver is capable of source 1.5A peak and sinking

2A peak. Initially, the diagonal HO1 and LO2 are turned-on together, followed by an off-time when all the four

gate driver outputs are off. In the subsequent phase the diagonal HO2 and LO1 are turned on together followed

by an off-time. The low-side gate drivers are powered directly by the VCC regulator. The HO1 and HO2 gate

drivers are powered from a bootstrap capacitor connected between BST1/BST2 and HS1/HS2 respectively. An

external diode connected between VCC (anode pin) and BST (cathode pin) provides the high side gate driver

power by charging the bootstrap capacitor from VCC when the corresponding switch node (HS1/HS2 pin) is low.

switch node voltage.

The BST and VCC capacitors should be placed close to the pins of the LM5045 to minimize voltage transients

due to parasitic inductances since the peak current sourced to the MOSFET gates can exceed 1.5A. The

recommended value of the BST capacitor is 0.1

μF or greater. A low ESR / ESL capacitor, such as a surface

mount ceramic, should be used to prevent voltage droop during the HO transitions.

If the COMP pin is open circuit, the outputs will operate at maximum duty cycle. The maximum duty cycle for

each phase is limited by the dead-time set by the RD1 resistor. If the RD1 resistor is set to zero then the

maximum duty cycle is slightly less than 50% due to the internally fixed dead-time. The internally fixed dead-time

is 30ns which does not vary with the operating frequency. The maximum duty cycle for each output can be

calculated from the following equation:

where

•

T1 is the time set by the RD1 resistor

•

(2)

For example, if the oscillator frequency is set at 400 kHz and the T1 time set by the RD1 resistor is 60ns, the

16

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