AM79C974 datasheet(44/153 Pages) AMD

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AMD

P R E L I M I N A R Y

Am79C974

rently has ownership of this ring descriptor and its

associated buffer. Only the owner is permitted to relin-

quish ownership or to write to any field in the descriptor

entry. A device that is not the current owner of a descrip-

tor entry cannot assume ownership or change any field

in the entry. A device may, however, read from a de-

scriptor that it does not currently own. Software should

always read descriptor entries in sequential order.

When software finds that the current descriptor is owned

by the Am79C974 controller, then the software must not

read “ahead” to the next descriptor. The software should

wait at the unOWNed descriptor until ownership has

been granted to the software (when LAPPEN = 1

(CSR3, bit 5), then this rule is modified. See the LAP-

PEN description). Strict adherence to these rules in-

sures that “Deadly Embrace” conditions are avoided.

Descriptor Ring Access Mechanism

At initialization, the Am79C974 controller reads the

base address of both the transmit and receive descriptor

rings into CSRs for use by the Am79C974 controller dur-

ing subsequent operations.

As the final step in the self-initialization process, the

base address of each ring is loaded into each of the cur-

rent descriptor address registers and the address of the

next descriptor entry in the transmit and receive rings is

computed and loaded into each of the next descriptor

address registers.

When SSIZE32 = 0, software data structures are 16 bits

wide. The following diagram, Figure 17, illustrates the

relationship between the Initialization Base Address,

the Initialization Block, the Receive and Transmit De-

scriptor Ring Base Addresses, the Receive and Trans-

mit Descriptors and the Receive and Transmit Data

Buffers, for the case of SSIZE32 = 0.

Initialization

Block

24-Bit Base Address

Pointer to

Initialization Block

IADR[15:0]

IADR[23:16]

RES

CSR1

CSR2

TDRA[15:0]

MODE

PADR[15:0]

PADR[31:16]

PADR[47:32]

LADRF[15:0]

LADRF[31:16]

LADRF[47:32]

LADRF[63:48]

RDRA[15:0]

RLEN

RES

RDRA[23:16]

TLEN

RES

TDRA[23:16]

Rcv

Buffers

RMD0

RMD1 RMD2 RMD3

Rcv Descriptor

Ring

•

1st desc.

start

2nd desc.

start

RMD0

Xmt

Buffers

RX DESCRIPTOR RINGS

TMD0

TMD1

TMD2

TMD3

RX DESCRIPTOR RINGS

Xmt Descriptor

Ring

•

1st desc.

start

2nd desc.

start

TMD0

Data

Buffer

Data

Buffer

Data

Buffer

Data

Buffer

Data

Buffer

Data

Buffer

18681A-21

Figure 17. 16-Bit Data Structures: Initialization Block and Descriptor Rings

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