AM79C974 datasheet(64/153 Pages) AMD

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AMD

P R E L I M I N A R Y

Am79C974

Hardware Access

PCnet-SCSI Controller Master Accesses

The Am79C974 controller has a bus interface compat-

ible with PCI specification revision 2.0.

Complete descriptions of the signals involved in bus

master transactions for each mode may be found in the

pin description section of this document. Timing dia-

grams for master accesses may be found in the block

description section for the Bus Interface Unit. This sec-

tion simply lists the types of master accesses that will be

performed by the Am79C974 controller with respect to

data size and address information.

The Am79C974 controller will support master accesses

only to 32-bit peripherals. The Am79C974 controller

does not support master accesses to 8-bit or 16-bit

memory. The Am79C974 controller is not compatible

with 8-bit systems, since there is no mode that supports

Am79C974 controller accesses to 8-bit peripherals.

Table 3 describes all possible bus master accesses that

the Am79C974 controller will perform. The right most

column lists all operations that may execute the given

access:

Table 3. Bus Master Accesses

Access

Mode

BE[3:0]

Operation

4-byte read

Read

0000

descriptor read

or initialization block read

or transmit data buffer read

4-byte write

Write

0000

descriptor write

or receive data buffer write

3-byte write

Write

1000

receive data buffer write

3-byte write

Write

0001

receive data buffer write

2-byte write

Write

1100

receive data buffer write

2-byte write

Write

1001*

receive data buffer write

2-byte write

Write

0011

receive data buffer write

1-byte write

Write

1110

receive data buffer write

1-byte write

Write

1101*

receive data buffer write

1-byte write

Write

1011*

receive data buffer write

1-byte write

Write

0111

descriptor write

or receive data buffer write

* Cases marked with an asterisk represent extreme boundary conditions that are the result of programming one- and two-byte

buffer sizes, and therefore will not be seen under normal circumstances.

Note that all Am79C974 controller master read opera-

tions will always activate all byte enables. Therefore, no

one-, two- or three-byte read operations are indicated in

the table.

In the instance where a transmit buffer pointer address

begins on a non-DWORD boundary, the pointer will be

truncated to the next DWORD boundary address that

lies below the given pointer address and the first read

access from the transmit buffer will be indicated on the

byte enable signals as a four-byte read from this ad-

dress. Any data from byte lanes that lie outside of the

boundary indicated by the buffer pointer will be dis-

carded inside of the Am79C974 controller. Similarly, if

the end of a transmit buffer occurs on a non-DWORD

boundary, then all byte lanes will be indicated as active

by the byte enable signals, and any data from byte lanes

that lie outside of the boundary indicated by the buffer

pointer will be discarded inside of the Am79C974

controller.

Slave Access to I/O Resources

The Am79C974 device is always a 32-bit peripheral on

the system bus. However, the width of individual soft-

ware resources on board the Am79C974 controller may

be either 16-bits or 32-bits. The Am79C974 controller

I/O resource widths are determined by the setting of the

DWIO bit as indicated in the following table:

Am79C974

Controller I/O

DWIO Setting Resource Width

Example Application

DWIO = 0

16-bit

Existing PCnet-ISA

driver that assumes

16-bit I/O mapping

and 16-bit resource

widths

DWIO = 1

32-bit

New drivers written

specifically for the

Am79C974 controller

AM79C974 Datasheet(PDF) 64 Page - Advanced Micro Devices

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