AM79C974 datasheet(19/153 Pages) AMD

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P R E L I M I N A R Y

AMD

Am79C974

PIN DESCRIPTION

PCI Bus Interface

AD[31:00]

Address and Data

Input/Output, Active High

These signals are multiplexed on the same PCI pins.

During the first clock of a transaction AD[31:00] contain

the physical byte address (32 bits). During the subse-

quent clocks AD[31:00] contain data. Byte ordering is lit-

tle endian by default. AD[07:00] are defined as least

significant byte and AD[31:24] are defined as the most

significant byte. For FIFO data transfers, the PCnet-

SCSI controller can be programmed for big endian byte

ordering. See CSR3, bit 2 (BSWP) for more details.

During the address phase of the transaction, when the

PCnet-SCSI controller is a bus master, AD[31:2] will ad-

dress the active DWORD (double-word). The PCnet-

SCSI controller always drives AD[1:0] to ‘00’ during the

address phase indicating linear burst order. When the

PCnet-SCSI controller is not a bus master, the

AD[31:00] lines are continuously monitored to deter-

mine if an address match exists for I/O slave transfers.

During the data phase of the transaction, AD[31:00] are

driven by the PCnet-SCSI controller when performing

bus master writes and slave read operations. Data on

AD[31:00] is latched by the PCnet-SCSI controller when

performing

bus

master

reads

and

slave

write

operations.

When

RST is active, AD[31:0] are inputs for NAND tree

testing.

C/BE [3:0]

Bus Command and Byte Enables

Input/Output, Active Low

These signals are multiplexed on the same PCI pins.

During the address phase of the transaction, C/

BE[3:0]

define the bus command. During the data phase

BE[3:0] are used as Byte Enables. The Byte Enables

define which physical byte lanes carry meaningful data.

BE0 applies to byte 0 (AD[07:00]) and C/BE3 applies

to byte 3 (AD[31:24]). The function of the Byte Enables

is independent of the byte ordering mode (CSR3, bit 2).

When

RST is active, C/BE[3:0] are inputs for NAND tree

testing.

CLK

Clock

Input

This signal provides timing for all the transactions on the

PCI bus and all PCI devices on the bus including the

PCnet-SCSI controller. All bus signals are sampled on

the rising edge of CLK and all parameters are defined

with respect to this edge. The PCnet-SCSI controller op-

erates over a range of 0 to 33 MHz.

When

RST is active, CLK is an input for NAND tree

testing.

DEVSEL

Device Select

Input/Output, Active Low

This signal when actively driven by the PCnet-SCSI

controller as a slave device signals to the master device

that the PCnet-SCSI controller has decoded its address

as the target of the current access. As an input it indi-

cates whether any device on the bus has been selected.

When

RST is active, DEVSEL is an input for NAND tree

testing.

FRAME

Cycle Frame

Input/Output, Active Low

This signal is driven by the PCnet-SCSI controller when

it is the bus master to indicate the beginning and dura-

tion of the access.

FRAME is asserted to indicate a bus

transaction is beginning.

FRAME is asserted while data

transfers continue.

FRAME is deasserted when the

transaction is in the final data phase.

When

RST is active, FRAME is an input for NAND tree

testing.

GNTA

Bus Grant

Input, Active Low

This signal indicates that the access to the bus has been

granted to the Am79C974’s SCSI controller.

The Am79C974 controller supports bus parking. When

the PCI bus is idle and the system arbiter asserts

GNTA

without an active

REQA from the Am79C974 controller,

the controller will actively drive the AD[31:00], C/

BE[3:0], and PAR lines.

When

RST is active, GNTA is an input for NAND tree

testing.

GNTB

Bus Grant

Input, Active Low

This signal indicates that the access to the bus has been

granted to the Am79C974’s Ethernet controller. The

Am79C974 controller supports bus parking. When the

PCI bus is idle and the system arbiter asserts

GNTB

without an active

REQB from the Am79C974 controller,

the controller will actively drive the AD, C/

BE and PAR

lines.

AM79C974 Datasheet(PDF) 19 Page - Advanced Micro Devices

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