TMS320C6745DPTP3 datasheet(7/227 Pages) TI

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TMS320C6745, TMS320C6747

www.ti.com

SPRS377E – SEPTEMBER 2008 – REVISED FEBRUARY 2013

Revision History (continued)

SEE

ADDITIONS/MODIFICATIONS/DELETIONS

Table 3-1, System Configuration (SYSCFG) Module Register Access:

Section 3.2

•

Updated/Changed 0x01C1 4018, DEVIDR0 REGISTER DESCRIPTION from “Device Identification

SYSCFG Module

•

Added 0x01C1 4024, CHIPREVID, Silicon Revision Identification Register row

Section 4.1, Absolute Maximum Ratings Over Operating Case Temperature Range:

Section 4

•

Updated/Changed Input voltage ranges, “VI I/O, CVDD" to "VI I/O, 1.2V"

Device Operating

•

Updated/Changed Input voltage ranges, VI I/O, 3.3V (Steady State) from “-0.3V to DVDD + 0.3V” to “-

Conditions

0.3V to DVDD + 0.35V”

Section 4.2, Recommended Operating Conditions:

•

Updated/Change DVDD, Supply voltage, I/O, 3.3V (DVDD, USB0_VDDA33, USB1_VDDA33) MIN value

from “3.15” to “3.0” V

Section 5.3.1, Power-on Sequence:

Section 5.3

Power Supplies

•

Updated/Changed, for clarity, the order the device should be powered-on

Section 5.5.1, Power-On Reset (POR):

Section 5.5

Reset

•

Updated/Changed "A power-on reset (POR) is required ..." paragraph

Section 5.5.2, Warm Reset:

•

Updated/Changed “A warm reset provides …” paragraph

Table 5-7, C6745/6747 DSP Interrupts:

Section 5.5

•

Updated/Changed EVT# 6, 17, 22, 35, 39, 44, 50, 66 from “RESERVED” to “PRU_EVTOUTx” where x

DSP Interrupts

is 0, 1, 3, 5, 6, 7, and 4, respectively

Table 5-7, C6745/6747 DSP Interrupts:

Section 5.8.1

•

Updated/Changed EVT# 74 INTERRUPT NAME from “PROTERR” to “MPU_BOOTCFG_ERR”

DSP Interrupts

•

Updated/Changed EVT# 74 SOURCE from “SYSCFG Protection Shared Interrupt” to “Shared MPU and

SYSCFG Address/Protection Error Interrupt"

Section 5.11

Section 5.11.4, EMIFA Connection Examples:

External Memory

•

Added new Subsection

Interface A (EMIFA)

Section 5.12

Figure 5-20, EMIFB Functional Block Diagram:

External Memory

•

Added MPU2 block to figure

Interface B (EMIFB)

Section 5.12.1, EMIFB SDRAM Loading Limitations:

•

Updated/Changed “EMIFB supports SDRAM up to 133MHz …” to “EMIFB supports SDRAM up to

152MHz …”

Table 5-28, EMIFB SDRAM Interface Switching Characteristics:

Section 5.12.3

•

Updated/Changed PARAMETER No. 1, tc(CLK) Cycle time, EMIF clock EMB_CLK MIN value from “7.5”

EMIFB Electrical

to “6.579” ns

Data/Timing

•

Updated/Changed PARAMETER No. 2, tw(CLK) Pulse width, EMIF clock EMB_CLK high or low MIN

value from “3” to “2.63” ns

Table 5-33, Switching Characteristics Over Recommended Operating Conditions for MMC/SD Module:

Section 5.14.3

MMC/SD Electrical

•

Updated/Changed the MAX value of PARAMETER No. 14, td(CLKL-DAT), Delay time, MMCSD_CLK low to

Data/Timing

MMCSD_DATx transition from “2” to “2.5” ns

Section 5.16.2

, Timing Requirements for MDIO Input:

Management Data

Input/Output (MDIO)

•

Updated/Changed the MIN value of No. 5, th(MDIO_CLKH-MDIO), Hold time, MDIO_D data input valid after

Electrical

MDIO_CLK high from “10” to “0” ns

Data/Timing

Table 5-55, General Timing Requirements for SPI0 Slave Modes:

Section 5.18.2

SPI Electrical

•

Updated/Changed MIN value of PARAMETER No. 9, tc(SPC)S, Cycle Time, SPI0_CLK, All Slave Modes

Data/Timing

from “greater of 3P or 20” to “greater of 3P or 40” ns

Section 5.22.1

Table 5-82, LCD LIDD Mode Timing Requirements:

LCD Interface

Table 5-83, LCD LIDD Mode Timing Characteristics:

Display Driver (LIDD

•

Updated/Changed LCD_CLK (SYSCLK2) all references to "LCD_MCLK"

Mode):

Contents

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