AD7682/AD7689

Data Sheet

Rev. D | Page 26 of 32

GENERAL TIMING WITHOUT A BUSY INDICATOR

Figure 37 details the timing for all three modes: read/write

during conversion (RDC), read/write after conversion (RAC),

and read/write spanning conversion (RSC). Note that the gating

item for both CFG and data readback is at the end of conversion

(EOC). At EOC, if CNV is high, the busy indicator is disabled.

As detailed previously in the Digital Interface section, the data

If the full CFG word was not written to prior to EOC, it is dis-

carded and the current configuration remains. If the conversion

result is not read out fully prior to EOC, it is lost as the ADC

updates SDO with the MSB of the current conversion. For

detailed timing, refer to Figure 40 and Figure 41, which depict

reading/writing spanning conversion with all timing details,

including setup, hold, and SCK.

When CNV is brought low after EOC, SDO is driven from high

impedance to the MSB. Falling SCK edges clock out bits starting

with MSB − 1.

The SCK can idle high or low depending on the clock polarity

(CPOL) and clock phase (CPHA) settings if SPI is used. A simple

solution is to use CPOL = CPHA = 0 as shown in Figure 37 with

SCK idling low.

From power-up, in any read/write mode, the first three conver-

sion results are undefined because a valid CFG does not take

required. Also, if the state machine writes the CFG during the

power-up state (RDC shown), the CFG register needs to be

rewritten again at the next phase. Note that the first valid data

occurs in Phase (n + 1) when the CFG register is written during

Phase (n − 1).

ACQUISITION

(n – 1) UNDEFINED

ACQUISITION

(n)

ACQUISITION

(n + 1)

ACQUISITION

(n + 2)

PHASE

POWER

UP

EOC

EOC

SOC

EOC

EOC

CONVERSION

(n – 1) UNDEFINED

CONVERSION

(n)

CONVERSION

(n + 1)

CONVERSION

(n – 2) UNDEFINED

CNV

CNV

CNV

DIN

SDO

XXX

MSB

XXX

MSB

XXX

NOTES

1. CNV MUST BE HIGH PRIOR TO THE END OF CONVERSION (EOC) TO AVOID THE BUSY INDICATOR.

2. A TOTAL OF 16 SCK FALLING EDGES ARE REQUIRED TO RETURN SDO TO HIGH-Z. IF CFG READBACK IS ENABLED, A TOTAL OF 30 SCK FALLING EDGES IS

REQUIRED TO RETURN SDO TO HIGH-Z.

DATA (n)

DATA (n – 1)

XXX

DATA (n – 1)

XXX

DATA (n – 1)

XXX

DATA (n – 1)

XXX

DATA (n – 2)

XXX

DATA (n – 2)

XXX

DATA (n – 2)

XXX

DATA (n – 2)

XXX

DATA (n – 3)

XXX

MSB

(n)

MSB

(n + 1)

DIN

SDO

DATA (n + 1)

DATA (n)

DATA (n)

DATA (n)

DATA (n + 1)

DIN

CFG (n)

CFG (n)

CFG (n + 2)

CFG (n + 2)

CFG (n + 1)

CFG (n + 1)

CFG (n + 3)

SDO

SCK

116

16

16

16

NOTE 2

NOTE 2

1

1

1

SCK

116

16

16

nn

n

n + 1

n + 1

n + 1

n

1

1

SCK

1

1

116

16

16

1

1

CFG (n)

CFG (n + 1)

CFG (n + 2)

RDC

RAC

RSC

CFG (n)

CFG (n + 1)

CFG (n + 2)

CFG (n + 3)

NOTE 2

NOTE 1

NOTE 1

NOTE 1

Figure 37. General Interface Timing for the AD7682/AD7689 Without a Busy Indicator