Data Sheet

AD7682/AD7689

Rev. D | Page 27 of 32

GENERAL TIMING WITH A BUSY INDICATOR

Figure 38 details the timing for all three modes: read/write

during conversion (RDC), read/write after conversion (RAC),

and read/write spanning conversion (RSC). Note that the gating

item for both CFG and data readback is at the end of conversion

(EOC). As detailed previously, the data access should occur up

not written to prior to EOC, it is discarded and the current

configuration remains.

At the EOC, if CNV is low, the busy indicator is enabled. In

addition, to generate the busy indicator properly, the host must

assert a minimum of 17 SCK falling edges to return SDO to high

impedance because the last bit on SDO remains active. Unlike the

case detailed in the Read/Write Spanning Conversion Without a

Busy Indicator section, if the conversion result is not read out

fully prior to EOC, the last bit clocked out remains. If this bit is

low, the busy signal indicator cannot be generated because the

busy generation requires either a high impedance or a remaining

bit high-to-low transition. A good example of this occurs when

an SPI host sends 16 SCKs because these are usually limited to

8-bit or 16-bit bursts; thus the LSB remains. Because the transi-

tion noise of the AD7682/AD7689 is 4 LSBs peak to peak (or

greater), the LSB is low 50% of the time. For this interface, the SPI

host needs to burst 24 SCKs, or a QSPI interface can be used and

programmed for 17 SCKs.

The SCK can idle high or low depending on the CPOL and

CPHA settings if SPI is used. A simple solution is to use CPOL =

CPHA = 1 (not shown) with SCK idling high.

From power-up, in any read/write mode, the first three conver-

sion results are undefined because a valid CFG does not take

required. Also, if the state machine writes the CFG during the

power-up state (RDC shown), the CFG register needs to be

rewritten again at the next phase. Note that the first valid data

occurs in Phase (n + 1) when the CFG register is written during

Phase (n − 1).

ACQUISITION

(n – 1) UNDEFINED

ACQUISITION

(n)

ACQUISITION

(n + 1)

ACQUISITION

(n + 2)

PHASE

POWER

UP

EOC

EOC

START OF CONVERSION

(SOC)

EOC

EOC

CONVERSION

(n)

CONVERSION

(n + 1)

CONVERSION

(n – 2) UNDEFINED

CNV

CNV

CNV

DIN

RDC

RAC

RSC

SDO

NOTES

1. CNV MUST BE LOW PRIOR TO THE END OF CONVERSION (EOC) TO GENERATE THE BUSY INDICATOR.

2. A TOTAL OF 17 SCK FALLING EDGES ARE REQUIRED TO RETURN SDO TO HIGH-Z. IF CFG READBACK IS ENABLED,

A TOTAL OF 31 SCK FALLING EDGES IS REQUIRED TO RETURN SDO TO HIGH-Z.

DATA (n)

DATA (n – 1)

XXX

DATA (n – 2)

XXX

DATA (n – 2)

XXX

DATA (n – 2)

XXX

DATA (n – 2)

XXX

DATA (n – 1)

XXX

DATA (n – 1)

XXX

DATA (n – 1)

XXX

DATA (n – 3)

XXX

DIN

SDO

DATA (n + 1)

DATA (n)

DATA (n)

DATA (n)

DATA (n + 1)

DIN

CFG (n)

CFG (n + 2)

CFG (n + 1)

CFG (n + 3)

SDO

SCK

1

1

1

1

SCK

1n

n + 1

17

17

17

17

17

17

17

17

1

n

n + 1

17

1

n

n + 1

17

SCK

1

1

1

1

1

XXX

NOTE 1

NOTE 1

NOTE 1

NOTE 2

NOTE 2

NOTE 2

CFG (n)

CFG (n + 1)

CFG (n + 2)

CFG (n)

CFG (n + 1)

CFG (n + 2)

CFG (n + 3)

CONVERSION

(n – 1) UNDEFINED

Figure 38. General Interface Timing for the AD7682/AD7689 With a Busy Indicator