COM20020ILJP datasheet(28/72 Pages) MICROCHIP

28 / 72 page

5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

Datasheet

Revision 12-05-06

Page 28

SMSC COM20020I Rev D

DATASHEET

New Next ID interrupt is cleared by reading the Next ID Register. The Interrupt Mask Register defaults to

the value 0000 0000 upon hardware reset.

6.2.2

Data Register

This read/write 8-bit register is used as the channel through which the data to and from the RAM passes.

The data is placed in or retrieved from the address location presently specified by the address pointer.

The contents of the Data Register are undefined upon hardware reset. In case of READ operation, the

Data Register is loaded with the contents of COM20020ID Internal Memory upon writing Address Pointer

low only once.

6.2.3

Tentative ID Register

The Tentative ID Register is a read/write 8-bit register accessed when the Sub Address Bits are set up

accordingly (please refer to the Configuration Register and SUB ADR Register). The Tentative ID Register

can be used while the node is on-line to build a network map of those nodes existing on the network. It

minimizes the need for operator interaction with the network. The node determines the existence of other

nodes by placing a Node ID value in the Tentative ID Register and waiting to see if the Tentative ID bit of

the Diagnostic Status Register gets set. The network map developed by this method is only valid for a

short period of time, since nodes may join or depart from the network at any time.

When using the

Tentative ID feature, a node cannot detect the existence of the next logical node to which it passes the

token. The Next ID Register will hold the ID value of that node. The Tentative ID Register defaults to the

value 0000 0000 upon hardware reset only.

6.2.4

Node ID Register

The Node ID Register is a read/write 8-bit register accessed when the Sub Address Bits are set up

accordingly (please refer to the Configuration Register and SUB ADR Register). The Node ID Register

contains the unique value which identifies this particular node. Each node on the network must have a

unique Node ID value at all times. The Duplicate ID bit of the Diagnostic Status Register helps the user

find a unique Node ID. Refer to the Initialization Sequence section for further detail on the use of the

DUPID bit. The core of the COM20020ID does not wake up until a Node ID other than zero is written into

the Node ID Register. During this time, no microcode is executed, no tokens are passed by this node, and

no reconfigurations are caused by this node.

Once a non-zero NodeID is placed into the Node ID

set. While the Transmitter is disabled, the Receiver portion of the device is still functional and will provide

the user with useful information about the network. The Node ID Register defaults to the value 0000 0000

upon hardware reset only.

6.2.5

Next ID Register

The Next ID Register is an 8-bit, read-only register, accessed when the sub-address bits are set up

accordingly (please refer to the Configuration Register and SUB ADR Register). The Next ID Register

holds the value of the Node ID to which the COM20020ID will pass the token. When used in conjunction

with the Tentative ID Register, the Next ID Register can provide a complete network map. The Next ID

Each time the microsequencer updates the Next ID Register, a New Next ID interrupt is generated. This bit

is cleared by reading the Next ID Register. Default value is 0000 0000 upon hardware or software reset.

COM20020ILJP Datasheet(PDF) 28 Page - Microchip Technology

COM20020ILJP Datasheet(HTML) 28 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72

Datasheet Download

Link URL