PIC18F242 datasheet(152/332 Pages) MICROCHIP

152 / 332 page

PIC18FXX2

DS39564C-page 150

15.4.6.1

I2C Master Mode Operation

The master device generates all of the serial clock

pulses and the START and STOP conditions. A trans-

fer is ended with a STOP condition or with a Repeated

START condition. Since the Repeated START condi-

tion is also the beginning of the next serial transfer, the

I2C bus will not be released.

In Master Transmitter mode, serial data is output

through SDA, while SCL outputs the serial clock. The

first byte transmitted contains the slave address of the

receiving device (7 bits) and the Read/Write (R/W) bit.

In this case, the R/W bit will be logic '0'. Serial data is

transmitted 8 bits at a time. After each byte is transmit-

ted, an Acknowledge bit is received. START and STOP

conditions are output to indicate the beginning and the

end of a serial transfer.

In Master Receive mode, the first byte transmitted con-

tains the slave address of the transmitting device

(7 bits) and the R/W bit. In this case, the R/W bit will be

logic '1'. Thus, the first byte transmitted is a 7-bit slave

address followed by a '1' to indicate receive bit. Serial

data is received via SDA, while SCL outputs the serial

clock. Serial data is received 8 bits at a time. After each

byte is received, an Acknowledge bit is transmitted.

START and STOP conditions indicate the beginning

and end of transmission.

The baud rate generator used for the SPI mode opera-

tion is used to set the SCL clock frequency for either

100 kHz, 400 kHz or 1 MHz I2C operation. See

Section 15.4.7 (“Baud Rate Generator”), for more

detail.

A typical transmit sequence would go as follows:

The user generates a START condition by set-

ting

the

START

enable

bit,

SEN

(SSPCON2<0>).

SSPIF is set. The MSSP module will wait the

required start time before any other operation

takes place.

The user loads the SSPBUF with the slave

address to transmit.

Address is shifted out the SDA pin until all 8 bits

are transmitted.

The MSSP Module shifts in the ACK bit from the

slave device and writes its value into the

SSPCON2 register (SSPCON2<6>).

The MSSP module generates an interrupt at the

end of the ninth clock cycle by setting the SSPIF

bit.

The user loads the SSPBUF with eight bits of

data.

Data is shifted out the SDA pin until all 8 bits are

transmitted.

The MSSP Module shifts in the ACK bit from the

slave device and writes its value into the

SSPCON2 register (SSPCON2<6>).

10. The MSSP module generates an interrupt at the

end of the ninth clock cycle by setting the SSPIF

bit.

11. The user generates a STOP condition by setting

the STOP enable bit PEN (SSPCON2<2>).

12. Interrupt is generated once the STOP condition

is complete.

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