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PIC18F242 Datasheet(PDF) 154 Page - Microchip Technology |
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PIC18F242 Datasheet(HTML) 154 Page - Microchip Technology |
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154 / 332 page ![]() PIC18FXX2 DS39564C-page 152 © 2006 Microchip Technology Inc. 15.4.7.1 Clock Arbitration Clock arbitration occurs when the master, during any receive, transmit or Repeated START/STOP condition, de-asserts the SCL pin (SCL allowed to float high). When the SCL pin is allowed to float high, the baud rate generator (BRG) is suspended from counting until the SCL pin is actually sampled high. When the SCL pin is sampled high, the baud rate generator is reloaded with the contents of SSPADD<6:0> and begins counting. This ensures that the SCL high time will always be at least one BRG rollover count, in the event that the clock is held low by an external device (Figure 15-18). FIGURE 15-18: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION SDA SCL SCL de-asserted but slave holds DX-1 DX BRG SCL is sampled high, reload takes place and BRG starts its count. 03h 02h 01h 00h (hold off) 03h 02h Reload BRG Value SCL low (clock arbitration) SCL allowed to transition high BRG decrements on Q2 and Q4 cycles |
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