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ATF1508AS Datasheet(PDF) 1 Page - ATMEL Corporation |
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ATF1508AS Datasheet(HTML) 1 Page - ATMEL Corporation |
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1 / 22 page  1 High Performance E 2 PLD ATF1508AS/Z Features • High Density, High Performance Electrically Erasable Complex Programmable Logic Device – 128 Macrocells – 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell – 68, 84, 100, 160-pins – 7.5 ns Maximum Pin-to-Pin Delay – Registered Operation Up To 125 MHz – Enhanced Routing Resources • Flexible Logic Macrocell – D/T/Latch Configurable Flip Flops – Global and Individual Register Control Signals – Global and Individual Output Enable – Programmable Output Slew Rate – Programmable Output Open Collector Option – Maximum Logic utilization by burying a register within a COM output • Advanced Power Management Features – Automatic 100 µµµµA Stand-By for “Z” Version (Max.) – Pin-Controlled 100 µµµµA Stand-By Mode (Typical) – Programmable Pin-Keeper Inputs and I/Os – Reduced-Power Feature Per Macrocell • Available in Commercial and Industrial Temperature Ranges • Available in 84-pin PLCC and 100-pin PQFP and TQFP and 160-pin PQFP Packages • Advanced Flash Technology – 100% Tested – Completely Reprogrammable – 100 Program/Erase Cycles – 20 Year Data Retention – 2000V ESD Protection – 200 mA Latch-Up Immunity • JTAG Boundary-Scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported • Fast In-System Programmability (ISP) via JTAG • PCI-compliant • 3.3 or 5.0V I/O pins • Security Fuse Feature Enhanced Features • Improved Connectivity (Additional Feedback Routing, Alternate Input Routing) • Output Enable Product Terms • D - Latch Mode • Combinatorial Output with Registered Feedback within any Macrocell • Three Global Clock Pins • ITD ( Input Transition Detection) Circuits on Global Clocks, Inputs and I/O • Fast Registered Input from Product Term • Programmable “Pin-Keeper” Option • V CC Power-Up Reset Option • Pull-Up Option on JTAG Pins TMS and TDI • Advanced Power Management Features – Edge Controlled Power Down “Z” – Individual Macrocell Power Option – Disable ITD on Global Clocks, Inputs and I/O for “Z” Parts Rev. 0784C–4/98 |
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