L99DZ70XP datasheet(7/47 Pages) STMICROELECTRONICS

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L99DZ70XP

Block diagram and pin description

Doc ID 15162 Rev 4

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OUT1,

OUT2,

OUT3

Halfbridge outputs 1,2,3.

The output is built by a highside and a lowside switch, which are internally

connected. The output stage of both switches is a power DMOS transistor.

Each driver has an internal parasitic reverse diode (bulk-drain-diode:

highside driver from output to VS, lowside driver from GND to output). This

output is over-current protected.

6, 7, 14, 15,

23, 24, 28,

Power supply voltage (external reverse protection required).

For this input a ceramic capacitor as close as possible to GND is

recommended.

Important: For the capability of driving the full current at the outputs all pins

of VS must be externally connected!

8DI

Serial data input.

The input requires CMOS logic levels and receives serial data from the

microcontroller. The data is a 24 bit control word and the most significant bit

(MSB, bit 23) is transferred first.

CM/

PWM2

Current monitor output/PWM2 input.

Depending on the selected multiplexer bits of the control register this output

sources an image of the instant current through the corresponding highside

driver with a ratio of 1/10.000 or 1/2000. This pin is bidirectional. The

microcontroller can overdrive the current monitor signal to provide a second

PWM input for the outputs OUT5, OUT8 and OUT10.

CSN

Chip Select Not input / Testmode.

This input is low active and requires CMOS logic levels. The serial data

transfer between L99DZ70 and the microcontroller is enabled by pulling the

input CSN to low level.

Serial data output.

The diagnosis data is available via the SPI and this tristate-output. The

output will remain in tristate, if the chip is not selected by the input CSN

(CSN = high)

VCC

Supply voltage.

For this input a ceramic capacitor as close as possible to GND is

recommended.

CLK

Serial clock input.

This input controls the internal shift register of the SPI and requires CMOS

logic levels.

16,17

20,21

OUT4,

OUT5,

OUT6

Halfbridge outputs 4,5,6: see OUT1 (pin 3).

Important: For the capability of driving the full current at the outputs both

pins of OUT4 (OUT5, respectively) must be externally connected!

ECDR

Electrocromic driver output.

If the electrochrome mode is selected this pin is used to control the gate of

an external MOSFET, otherwise it remains in high-impedance state.

Note: It is possible to connect the pin to VS as in L9950/53/54 applications,

as long as the electrochome mode is not enabled via SPI.

Charge pump output.

This output is provided to drive the gate of an external n-channel power

MOS used for reverse polarity protection (see Figure 1.).

Table 2.

Pin definition and functions (continued)

Symbol

Function

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