MA1916

4/11

SMC_OUT (Select Message or Checksum)

This output signal is held high while the test generator clocks

out a data packet on the MSG_OUT pin. When the packet is

complete this signal goes low. It is held low for a period equal to

the time required by the RS encoder to send the corresponding

checksum. When this is complete the signal goes high and the

test generator begins a new data packet. This signal can be

connected directly to SMC for testing purposes.

READY (Test Data Valid)

This output is held low during reset and remains low for the

first complete cycle of SMC_OUT. READY rises on the second

rising edge of SMC_OUT and remains high to indicate the

presence of valid data on MSG_OUT.

CLKS (Synchronisation Clock)

This output clock runs at half the speed of the input clock

CLK. CLKS remains low after n_RST is raised until SMC is

raised, SMC being captured on the falling edge of CLK (timing

4). CLKS then changes state on the rising edge of each CLK

cycle regardless of the state of SMC. The signal is used to

clock data into and out of the RS encoder.

MSG (Message)

MSG is the data input to the RS encoder. Each bit is read in

on the rising edge of CLKS. While the SMC signal is high data

on the input passes directly to the output RSE_OUT. While

SMC is low RSE_OUT is the logical XOR of the MSG input and

the output of the check-sum generator. Therefore MSG must

be held low while the RS encoder is clocking out the check

sum (see Figure 4).

SMC (Select Message or Checksum)

While the SMC input is high, data on the MSG pin is

clocked into the RS encoder. SMC is held high for a period

dictated by the interleave depth being used (see Table 1).

When SMC falls the RS encoder begins to clock out the

checksum for the preceeding data. SMC should be held low

until the complete checksum has been output. The rising edge

of SMC indicates the start of a new data block to be encoded.

RSE_OUT (Reed-Solomon Encoder Output)

This signal outputs the completed data packet comprised

of the message followed by its associated checksum block.

The data is valid on the rising edge of CLKS.

Figure 4: Reed-Solomon Encoder

ST1 (RS Encoder Output Valid)

This output is set low during a reset and goes high when

sufficient dummy data has been clocked through the RS

encoder to clear it (see Figure 5).

SYZ (Byte Rate Clock)

SYZ is a byte rate clock output derived from CLKS. It is

high during every eighth period of CLKS and low at other

times.

SZY (Byte Rate Clock)

SZY is a byte rate clock output derived from CLKS. It is low

during every eighth period of CLKS and high at other times. It

is the inverse of SYZ.

ST2 (Production Test Output)

The output is used for production testing and should be left

unconnected.

TEST_POINT (Production Test Output)

This output is used for production testing and should be left

unconnected.

CE_IN (Convolution Encoder Data In)

This input is used to read data into the convolution

encoder. The state of CE_IN is read on the rising edge of

CE_CLK.

Figure 5: Reed-Solomon Encoder Operation

SMC

MSG

CLKS

ST1

n_RST

Output Valid

Note: ST1 rises on the second rising edge of SMC following n_RST high.

CLKS starts toggling on the first rising edge of SMC following n_RST high.